main_fbas Project Status (04/28/2016 - 14:55:05)
Project File: main.xise Parser Errors: No Errors
Module Name: main_fbas Implementation State: Programming File Generated
Target Device: xc3s400-4tq144
  • Errors:
No Errors
Product Version:ISE 14.7
  • Warnings:
33 Warnings (0 new)
Design Goal: Balanced
  • Routing Results:
All Signals Completely Routed
Design Strategy: Xilinx Default (unlocked)
  • Timing Constraints:
All Constraints Met
Environment: System Settings
  • Final Timing Score:
0  (Timing Report)
 
Device Utilization Summary [-]
Logic UtilizationUsedAvailableUtilizationNote(s)
Number of Slice Flip Flops 124 7,168 1%  
Number of 4 input LUTs 201 7,168 2%  
Number of occupied Slices 125 3,584 3%  
    Number of Slices containing only related logic 125 125 100%  
    Number of Slices containing unrelated logic 0 125 0%  
Total Number of 4 input LUTs 219 7,168 3%  
    Number used as logic 199      
    Number used as a route-thru 18      
    Number used as Shift registers 2      
Number of bonded IOBs 11 97 11%  
Number of BUFGMUXs 5 8 62%  
Average Fanout of Non-Clock Nets 3.16      
 
Performance Summary [-]
Final Timing Score: 0 (Setup: 0, Hold: 0) Pinout Data: Pinout Report
Routing Results: All Signals Completely Routed Clock Data: Clock Report
Timing Constraints: All Constraints Met    
 
Detailed Reports [-]
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis ReportCurrentDo 28. Apr 16:17:16 2016030 Warnings (0 new)0
Translation ReportCurrentDo 28. Apr 16:17:26 2016000
Map ReportCurrentDo 28. Apr 16:17:32 2016004 Infos (0 new)
Place and Route ReportCurrentDo 28. Apr 16:17:44 201603 Warnings (0 new)2 Infos (0 new)
Power Report     
Post-PAR Static Timing ReportCurrentDo 28. Apr 16:17:48 2016006 Infos (0 new)
Bitgen ReportCurrentDo 28. Apr 16:17:55 2016001 Info (0 new)
 
Secondary Reports [-]
Report NameStatusGenerated
WebTalk ReportCurrentDo 28. Apr 16:17:56 2016
WebTalk Log FileCurrentDo 28. Apr 16:18:02 2016

Date Generated: 06/01/2016 - 10:07:51