Release 14.7 - xst P.20131013 (nt64) Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. --> Parameter TMPDIR set to xst/projnav.tmp Total REAL time to Xst completion: 0.00 secs Total CPU time to Xst completion: 0.13 secs --> Parameter xsthdpdir set to xst Total REAL time to Xst completion: 0.00 secs Total CPU time to Xst completion: 0.13 secs --> Reading design: fbas_count.prj TABLE OF CONTENTS 1) Synthesis Options Summary 2) HDL Compilation 3) Design Hierarchy Analysis 4) HDL Analysis 5) HDL Synthesis 5.1) HDL Synthesis Report 6) Advanced HDL Synthesis 6.1) Advanced HDL Synthesis Report 7) Low Level Synthesis 8) Partition Report 9) Final Report 9.1) Device utilization summary 9.2) Partition Resource Summary 9.3) TIMING REPORT ========================================================================= * Synthesis Options Summary * ========================================================================= ---- Source Parameters Input File Name : "fbas_count.prj" Input Format : mixed Ignore Synthesis Constraint File : NO ---- Target Parameters Output File Name : "fbas_count" Output Format : NGC Target Device : xc3s400-4-tq144 ---- Source Options Top Module Name : fbas_count Automatic FSM Extraction : YES FSM Encoding Algorithm : Auto Safe Implementation : No FSM Style : LUT RAM Extraction : Yes RAM Style : Auto ROM Extraction : Yes Mux Style : Auto Decoder Extraction : YES Priority Encoder Extraction : Yes Shift Register Extraction : YES Logical Shifter Extraction : YES XOR Collapsing : YES ROM Style : Auto Mux Extraction : Yes Resource Sharing : YES Asynchronous To Synchronous : NO Multiplier Style : Auto Automatic Register Balancing : No ---- Target Options Add IO Buffers : YES Global Maximum Fanout : 100000 Add Generic Clock Buffer(BUFG) : 8 Register Duplication : YES Slice Packing : YES Optimize Instantiated Primitives : NO Use Clock Enable : Yes Use Synchronous Set : Yes Use Synchronous Reset : Yes Pack IO Registers into IOBs : Auto Equivalent register Removal : YES ---- General Options Optimization Goal : Speed Optimization Effort : 1 Keep Hierarchy : No Netlist Hierarchy : As_Optimized RTL Output : Yes Global Optimization : AllClockNets Read Cores : YES Write Timing Constraints : NO Cross Clock Analysis : NO Hierarchy Separator : / Bus Delimiter : <> Case Specifier : Maintain Slice Utilization Ratio : 100 BRAM Utilization Ratio : 100 Verilog 2001 : YES Auto BRAM Packing : NO Slice Utilization Ratio Delta : 5 ========================================================================= WARNING:Xst:2682 - Unable to write in file "fbas_count.lso" ========================================================================= * HDL Compilation * ========================================================================= Compiling vhdl file "E:/Dropbox/CTLAB_FBAS/fbas_sync.vhdl" in Library work. Architecture behavioral of Entity fbas_count is up to date. ========================================================================= * Design Hierarchy Analysis * ========================================================================= Analyzing hierarchy for entity in library (architecture ). ========================================================================= * HDL Analysis * ========================================================================= Analyzing Entity in library (Architecture ). Entity analyzed. Unit generated. ========================================================================= * HDL Synthesis * ========================================================================= Performing bidirectional port resolution... Synthesizing Unit . Related source file is "E:/Dropbox/CTLAB_FBAS/fbas_sync.vhdl". Found 6-bit up counter for signal . Found 1-bit register for signal . Found 16-bit up counter for signal . Found 16-bit up counter for signal . Found 1-bit xor2 for signal created at line 51. Found 1-bit register for signal . Found 1-bit register for signal . Found 1-bit register for signal . Found 1-bit xor2 for signal created at line 86. Found 1-bit register for signal . Found 1-bit register for signal . Summary: inferred 3 Counter(s). inferred 6 D-type flip-flop(s). Unit synthesized. ========================================================================= HDL Synthesis Report Macro Statistics # Counters : 3 16-bit up counter : 2 6-bit up counter : 1 # Registers : 6 1-bit register : 6 # Xors : 2 1-bit xor2 : 2 ========================================================================= ========================================================================= * Advanced HDL Synthesis * ========================================================================= ========================================================================= Advanced HDL Synthesis Report Macro Statistics # Counters : 3 16-bit up counter : 2 6-bit up counter : 1 # Registers : 6 Flip-Flops : 6 # Xors : 2 1-bit xor2 : 2 ========================================================================= ========================================================================= * Low Level Synthesis * ========================================================================= Optimizing unit ... Mapping all equations... Building and optimizing final netlist ... Found area constraint ratio of 100 (+ 5) on block fbas_count, actual ratio is 1. FlipFlop clk_int_tick has been replicated 1 time(s) Final Macro Processing ... ========================================================================= Final Register Report Macro Statistics # Registers : 45 Flip-Flops : 45 ========================================================================= ========================================================================= * Partition Report * ========================================================================= Partition Implementation Status ------------------------------- No Partitions were found in this design. ------------------------------- ========================================================================= * Final Report * ========================================================================= Final Results RTL Top Level Output File Name : fbas_count.ngr Top Level Output File Name : fbas_count Output Format : NGC Optimization Goal : Speed Keep Hierarchy : No Design Statistics # IOs : 5 Cell Usage : # BELS : 143 # GND : 1 # INV : 3 # LUT1 : 30 # LUT2 : 4 # LUT2_D : 1 # LUT2_L : 4 # LUT3 : 7 # LUT3_D : 3 # LUT4 : 21 # LUT4_D : 2 # LUT4_L : 4 # MUXCY : 30 # VCC : 1 # XORCY : 32 # FlipFlops/Latches : 45 # FDE : 5 # FDR : 8 # FDRE : 32 # Clock Buffers : 1 # BUFGP : 1 # IO Buffers : 4 # OBUF : 4 ========================================================================= Device utilization summary: --------------------------- Selected Device : 3s400tq144-4 Number of Slices: 40 out of 3584 1% Number of Slice Flip Flops: 45 out of 7168 0% Number of 4 input LUTs: 79 out of 7168 1% Number of IOs: 5 Number of bonded IOBs: 5 out of 97 5% Number of GCLKs: 1 out of 8 12% --------------------------- Partition Resource Summary: --------------------------- No Partitions were found in this design. --------------------------- ========================================================================= TIMING REPORT NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE. FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT GENERATED AFTER PLACE-and-ROUTE. Clock Information: ------------------ -----------------------------------+------------------------+-------+ Clock Signal | Clock buffer(FF name) | Load | -----------------------------------+------------------------+-------+ SYSCLK | BUFGP | 45 | -----------------------------------+------------------------+-------+ Asynchronous Control Signals Information: ---------------------------------------- No asynchronous control signals found in this design Timing Summary: --------------- Speed Grade: -4 Minimum period: 7.903ns (Maximum Frequency: 126.534MHz) Minimum input arrival time before clock: No path found Maximum output required time after clock: 9.038ns Maximum combinational path delay: No path found Timing Detail: -------------- All values displayed in nanoseconds (ns) ========================================================================= Timing constraint: Default period analysis for Clock 'SYSCLK' Clock period: 7.903ns (frequency: 126.534MHz) Total number of paths / destination ports: 1576 / 120 ------------------------------------------------------------------------- Delay: 7.903ns (Levels of Logic = 3) Source: count_h_14 (FF) Destination: count_h_0 (FF) Source Clock: SYSCLK rising Destination Clock: SYSCLK rising Data Path: count_h_14 to count_h_0 Gate Net Cell:in->out fanout Delay Delay Logical Name (Net Name) ---------------------------------------- ------------ FDRE:C->Q 2 0.720 1.216 count_h_14 (count_h_14) LUT4:I0->O 1 0.551 0.996 count_h_cmp_eq0000123 (count_h_cmp_eq0000123) LUT3:I1->O 5 0.551 0.947 count_h_cmp_eq0000143 (N2) LUT4:I3->O 17 0.551 1.345 count_h_and00001 (count_h_and0000) FDRE:R 1.026 count_h_0 ---------------------------------------- Total 7.903ns (3.399ns logic, 4.504ns route) (43.0% logic, 57.0% route) ========================================================================= Timing constraint: Default OFFSET OUT AFTER for Clock 'SYSCLK' Total number of paths / destination ports: 11 / 4 ------------------------------------------------------------------------- Offset: 9.038ns (Levels of Logic = 2) Source: video_on_v (FF) Destination: VIDEO<2> (PAD) Source Clock: SYSCLK rising Data Path: video_on_v to VIDEO<2> Gate Net Cell:in->out fanout Delay Delay Logical Name (Net Name) ---------------------------------------- ------------ FDE:C->Q 2 0.720 1.216 video_on_v (video_on_v) LUT3:I0->O 3 0.551 0.907 VIDEO<1>1 (VIDEO_1_OBUF) OBUF:I->O 5.644 VIDEO_2_OBUF (VIDEO<2>) ---------------------------------------- Total 9.038ns (6.915ns logic, 2.123ns route) (76.5% logic, 23.5% route) ========================================================================= Total REAL time to Xst completion: 11.00 secs Total CPU time to Xst completion: 11.66 secs --> Total memory usage is 260772 kilobytes Number of errors : 0 ( 0 filtered) Number of warnings : 1 ( 0 filtered) Number of infos : 0 ( 0 filtered)