library IEEE;

use IEEE.std_logic_1164.all;

use IEEE.std_logic_arith.all;

use IEEE.std_logic_unsigned.all;

use IEEE.numeric_std.all;

 

entity chipIO is

  

   port(

      pin_sysclk  : in std_logic;                      -- master clock from external clock source
     

      -- vga port connections

      pin_vga_red0     : out std_logic;

      pin_vga_red1     : out std_logic;

      pin_vga_green0   : out std_logic;

      pin_vga_green1   : out std_logic;

      pin_vga_blue0    : out std_logic;

      pin_vga_blue1    : out std_logic;

      pin_vga_hsync_n  : out std_logic;

      pin_vga_vsync_n  : out std_logic

 

   );

  

end chipIO;

 

architecture arch of chipIO is

 

         constant YES:         std_logic := '1';

         constant NO:          std_logic := '0';

         constant HI:            std_logic := '1';

         constant LO:           std_logic := '0';

 

   signal sysClk   : std_logic;  -- system clock

   signal sysReset : std_logic;  -- system reset

 

         component VGA_SYNC

                         port(

                         clk50_in : in std_logic;

                         red, green, blue : in std_logic;

                         red_out, green_out, blue_out : out std_logic;

                         horiz_sync_out, vert_sync_out : out std_logic;

                         pixel_row, pixel_column : out std_logic_vector(9 downto 0));

         end component;

 

         signal vga_pixel_row     : std_logic_vector(9 downto 0);

         signal vga_pixel_column  : std_logic_vector(9 downto 0);

         signal vga_vert_sync_out : std_logic;

 

         component ball

         port(

         signal red,green,blue : OUT std_logic;

                         signal vert_sync_out : in std_logic;

                         signal pixel_row, pixel_column : in std_logic_vector(9 downto 0));

         end component;

 

         signal ball_red   : std_logic;

         signal ball_green : std_logic;

         signal ball_blue  : std_logic;

 

begin

 


   -- define system clock and reset

   sysClk   <= pin_sysclk;

 

   pin_vga_red0   <= '0';

         pin_vga_green0 <= '0';

         pin_vga_blue0  <= '0';

 

 

   --

   -- CREATE COMPONENTS

   --

 

         vgadriver:

                         VGA_SYNC

                         port map(

                         clk50_in    => sysClk,

                         red            => ball_red,

                         green          => ball_green,

                         blue           => ball_blue,

                         red_out        => pin_vga_red1,

                         green_out      => pin_vga_green1,

                         blue_out       => pin_vga_blue1,

                         horiz_sync_out => pin_vga_hsync_n,

                         vert_sync_out  => vga_vert_sync_out,

                         pixel_row      => vga_pixel_row,

                         pixel_column   => vga_pixel_column

                         );

 

         pin_vga_vsync_n <= vga_vert_sync_out;

 

         balldriver:

          ball

         port map(

         red            => ball_red,

         green          => ball_green,

         blue           => ball_blue,

                         vert_sync_out  => vga_vert_sync_out,

                         pixel_row      => vga_pixel_row,

                         pixel_column   => vga_pixel_column

                         );

  

end arch;