main Project Status (06/29/2009 - 08:22:53)
Project File:	main.ise	Current State:	Programming File Generated
Module Name:	main_test	Errors:	No Errors
Target Device:	xc3s400-4tq144	Warnings:	209 Warnings
Product Version:	ISE 10.1.03 - WebPACK	Routing Results:	All Signals Completely Routed
Design Goal:	Balanced	Timing Constraints:	All Constraints Met
Design Strategy:	Xilinx Default (unlocked)	Final Timing Score:	0 (Timing Report)

 

main Partition Summary				[-]
No partition information was found.

 

Device Utilization Summary					[-]
Logic Utilization	Used	Available	Utilization	Note(s)
Total Number Slice Registers	423	7,168	5%
Number used as Flip Flops	422
Number used as Latches	1
Number of 4 input LUTs	478	7,168	6%
Logic Distribution
Number of occupied Slices	386	3,584	10%
Number of Slices containing only related logic	386	386	100%
Number of Slices containing unrelated logic	0	386	0%
Total Number of 4 input LUTs	546	7,168	7%
Number used as logic	478
Number used as a route-thru	68
Number of bonded IOBs
Number of bonded	18	97	18%
Number of RAMB16s	9	16	56%
Number of BUFGMUXs	6	8	75%

 

Performance Summary				[-]
Final Timing Score:	0	Pinout Data:	Pinout Report
Routing Results:	All Signals Completely Routed	Clock Data:	Clock Report
Timing Constraints:	All Constraints Met

 

Detailed Reports						[-]
Report Name	Status	Generated	Errors	Warnings	Infos
Synthesis Report	Current	Mo 29. Jun 08:22:14 2009	0	189 Warnings	3 Infos
Translation Report	Current	Mo 29. Jun 08:22:19 2009	0	6 Warnings	0
Map Report	Current	Mo 29. Jun 08:22:24 2009	0	3 Warnings	3 Infos
Place and Route Report	Current	Mo 29. Jun 08:22:44 2009	0	11 Warnings	3 Infos
Static Timing Report	Current	Mo 29. Jun 08:22:47 2009	0	0	3 Infos
Bitgen Report	Current	Mo 29. Jun 08:22:52 2009	0	1 Warning	1 Info

Date Generated: 06/29/2009 - 09:22:39