-------------------------------------------------------------------------------- -- Copyright (c) 1995-2003 Xilinx, Inc. -- All Right Reserved. -------------------------------------------------------------------------------- -- ____ ____ -- / /\/ / -- /___/ \ / Vendor: Xilinx -- \ \ \/ Version : 10.1.03 -- \ \ Application : ISE -- / / Filename : COUNT_LRC_tb.ant -- /___/ /\ Timestamp : Mon Mar 09 00:05:01 2009 -- \ \ / \ -- \___\/\___\ -- --Command: --Design Name: COUNT_LRC_tb --Device: Xilinx -- library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; use ieee.numeric_std.all; USE IEEE.STD_LOGIC_TEXTIO.ALL; USE IEEE.STD_LOGIC_ARITH.ALL; USE STD.TEXTIO.ALL; ENTITY COUNT_LRC_tb IS END COUNT_LRC_tb; ARCHITECTURE testbench_arch OF COUNT_LRC_tb IS FILE RESULTS: TEXT OPEN WRITE_MODE IS "D:\ProjFPGA\ct-Atom\main\COUNT_LRC_tb.ano"; COMPONENT COUNT_LRC PORT ( LC_ADDR : Out std_logic_vector (18 DownTo 0); SYSCLK : In std_logic; LOADRST : In std_logic; READRST : In std_logic; RAMINCR : In std_logic; ENARST : In std_logic; START : In std_logic_vector (18 DownTo 0); LC_ENA : Out std_logic; LC_WEN : Out std_logic; LC_OEN : Out std_logic ); END COMPONENT; SIGNAL LC_ADDR : std_logic_vector (18 DownTo 0) := "0000000000000000000"; SIGNAL SYSCLK : std_logic := '0'; SIGNAL LOADRST : std_logic := '0'; SIGNAL READRST : std_logic := '0'; SIGNAL RAMINCR : std_logic := '0'; SIGNAL ENARST : std_logic := '0'; SIGNAL START : std_logic_vector (18 DownTo 0) := "0000000000000000000"; SIGNAL LC_ENA : std_logic := '0'; SIGNAL LC_WEN : std_logic := '0'; SIGNAL LC_OEN : std_logic := '0'; SHARED VARIABLE TX_ERROR : INTEGER := 0; SHARED VARIABLE TX_OUT : LINE; constant PERIOD : time := 20 ns; constant DUTY_CYCLE : real := 0.5; constant OFFSET : time := 2 ns; BEGIN UUT : COUNT_LRC PORT MAP ( LC_ADDR => LC_ADDR, SYSCLK => SYSCLK, LOADRST => LOADRST, READRST => READRST, RAMINCR => RAMINCR, ENARST => ENARST, START => START, LC_ENA => LC_ENA, LC_WEN => LC_WEN, LC_OEN => LC_OEN ); PROCESS -- clock process for SYSCLK BEGIN WAIT for OFFSET; CLOCK_LOOP : LOOP SYSCLK <= '0'; WAIT FOR (PERIOD - (PERIOD * DUTY_CYCLE)); SYSCLK <= '1'; WAIT FOR (PERIOD * DUTY_CYCLE); END LOOP CLOCK_LOOP; END PROCESS; PROCESS -- Annotation process for SYSCLK VARIABLE TX_TIME : INTEGER := 0; PROCEDURE ANNOTATE_LC_ADDR( TX_TIME : INTEGER ) IS VARIABLE TX_STR : String(1 to 4096); VARIABLE TX_LOC : LINE; BEGIN STD.TEXTIO.write(TX_LOC, string'("Annotate[")); STD.TEXTIO.write(TX_LOC, TX_TIME); STD.TEXTIO.write(TX_LOC, string'(", LC_ADDR, ")); IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, LC_ADDR); STD.TEXTIO.write(TX_LOC, string'("]")); TX_STR(TX_LOC.all'range) := TX_LOC.all; STD.TEXTIO.writeline(RESULTS, TX_LOC); STD.TEXTIO.Deallocate(TX_LOC); END; PROCEDURE ANNOTATE_LC_ENA( TX_TIME : INTEGER ) IS VARIABLE TX_STR : String(1 to 4096); VARIABLE TX_LOC : LINE; BEGIN STD.TEXTIO.write(TX_LOC, string'("Annotate[")); STD.TEXTIO.write(TX_LOC, TX_TIME); STD.TEXTIO.write(TX_LOC, string'(", LC_ENA, ")); IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, LC_ENA); STD.TEXTIO.write(TX_LOC, string'("]")); TX_STR(TX_LOC.all'range) := TX_LOC.all; STD.TEXTIO.writeline(RESULTS, TX_LOC); STD.TEXTIO.Deallocate(TX_LOC); END; PROCEDURE ANNOTATE_LC_WEN( TX_TIME : INTEGER ) IS VARIABLE TX_STR : String(1 to 4096); VARIABLE TX_LOC : LINE; BEGIN STD.TEXTIO.write(TX_LOC, string'("Annotate[")); STD.TEXTIO.write(TX_LOC, TX_TIME); STD.TEXTIO.write(TX_LOC, string'(", LC_WEN, ")); IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, LC_WEN); STD.TEXTIO.write(TX_LOC, string'("]")); TX_STR(TX_LOC.all'range) := TX_LOC.all; STD.TEXTIO.writeline(RESULTS, TX_LOC); STD.TEXTIO.Deallocate(TX_LOC); END; PROCEDURE ANNOTATE_LC_OEN( TX_TIME : INTEGER ) IS VARIABLE TX_STR : String(1 to 4096); VARIABLE TX_LOC : LINE; BEGIN STD.TEXTIO.write(TX_LOC, string'("Annotate[")); STD.TEXTIO.write(TX_LOC, TX_TIME); STD.TEXTIO.write(TX_LOC, string'(", LC_OEN, ")); IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, LC_OEN); STD.TEXTIO.write(TX_LOC, string'("]")); TX_STR(TX_LOC.all'range) := TX_LOC.all; STD.TEXTIO.writeline(RESULTS, TX_LOC); STD.TEXTIO.Deallocate(TX_LOC); END; BEGIN WAIT for 1 fs; ANNOTATE_LC_ADDR(0); ANNOTATE_LC_ENA(0); ANNOTATE_LC_WEN(0); ANNOTATE_LC_OEN(0); WAIT for OFFSET; TX_TIME := TX_TIME + 2; ANNO_LOOP : LOOP --Rising Edge WAIT for 15 ns; TX_TIME := TX_TIME + 15; ANNOTATE_LC_ADDR(TX_TIME); ANNOTATE_LC_ENA(TX_TIME); ANNOTATE_LC_WEN(TX_TIME); ANNOTATE_LC_OEN(TX_TIME); WAIT for 5 ns; TX_TIME := TX_TIME + 5; END LOOP ANNO_LOOP; END PROCESS; PROCESS BEGIN -- ------------- Current Time: 107ns WAIT FOR 107 ns; LOADRST <= '1'; -- ------------------------------------- -- ------------- Current Time: 147ns WAIT FOR 40 ns; LOADRST <= '0'; -- ------------------------------------- -- ------------- Current Time: 327ns WAIT FOR 180 ns; RAMINCR <= '1'; -- ------------------------------------- -- ------------- Current Time: 347ns WAIT FOR 20 ns; RAMINCR <= '0'; -- ------------------------------------- -- ------------- Current Time: 567ns WAIT FOR 220 ns; RAMINCR <= '1'; -- ------------------------------------- -- ------------- Current Time: 607ns WAIT FOR 40 ns; RAMINCR <= '0'; -- ------------------------------------- -- ------------- Current Time: 887ns WAIT FOR 280 ns; ENARST <= '1'; -- ------------------------------------- -- ------------- Current Time: 927ns WAIT FOR 40 ns; ENARST <= '0'; -- ------------------------------------- -- ------------- Current Time: 1067ns WAIT FOR 140 ns; READRST <= '1'; -- ------------------------------------- -- ------------- Current Time: 1107ns WAIT FOR 40 ns; READRST <= '0'; -- ------------------------------------- -- ------------- Current Time: 1287ns WAIT FOR 180 ns; RAMINCR <= '1'; -- ------------------------------------- -- ------------- Current Time: 1307ns WAIT FOR 20 ns; RAMINCR <= '0'; -- ------------------------------------- -- ------------- Current Time: 1487ns WAIT FOR 180 ns; RAMINCR <= '1'; -- ------------------------------------- -- ------------- Current Time: 1527ns WAIT FOR 40 ns; RAMINCR <= '0'; -- ------------------------------------- -- ------------- Current Time: 1707ns WAIT FOR 180 ns; ENARST <= '1'; -- ------------------------------------- -- ------------- Current Time: 1747ns WAIT FOR 40 ns; ENARST <= '0'; -- ------------------------------------- WAIT FOR 273 ns; STD.TEXTIO.write(TX_OUT, string'("Total[]")); STD.TEXTIO.writeline(RESULTS, TX_OUT); ASSERT (FALSE) REPORT "Success! Simulation for annotation completed" SEVERITY FAILURE; END PROCESS; END testbench_arch;