-------------------------------------------------------------------------------- -- Copyright (c) 1995-2008 Xilinx, Inc. All rights reserved. -------------------------------------------------------------------------------- -- ____ ____ -- / /\/ / -- /___/ \ / Vendor: Xilinx -- \ \ \/ Version : 10.1.03 -- \ \ Application : sch2vhdl -- / / Filename : GTEXT_LCD320.vhf -- /___/ /\ Timestamp : 11/03/2009 12:44:17 -- \ \ / \ -- \___\/\___\ -- --Command: C:\Xilinx\10.1\ISE\bin\nt\unwrapped\sch2vhdl.exe -intstyle ise -family spartan3 -flat -suppress -w E:/ProjFPGA/ct-BASIC-LCD/source/GTEXT_LCD320.sch GTEXT_LCD320.vhf --Design Name: GTEXT_LCD320 --Device: spartan3 --Purpose: -- This vhdl netlist is translated from an ECS schematic. It can be -- synthesis and simulted, but it should not be modified. -- library ieee; use ieee.std_logic_1164.ALL; use ieee.numeric_std.ALL; library UNISIM; use UNISIM.Vcomponents.ALL; entity FTCE_MXILINX_GTEXT_LCD320 is port ( C : in std_logic; CE : in std_logic; CLR : in std_logic; T : in std_logic; Q : out std_logic); end FTCE_MXILINX_GTEXT_LCD320; architecture BEHAVIORAL of FTCE_MXILINX_GTEXT_LCD320 is attribute BOX_TYPE : string ; attribute INIT : string ; attribute RLOC : string ; signal TQ : std_logic; signal Q_DUMMY : std_logic; component XOR2 port ( I0 : in std_logic; I1 : in std_logic; O : out std_logic); end component; attribute BOX_TYPE of XOR2 : component is "BLACK_BOX"; component FDCE -- synopsys translate_off generic( INIT : bit := '0'); -- synopsys translate_on port ( C : in std_logic; CE : in std_logic; CLR : in std_logic; D : in std_logic; Q : out std_logic); end component; attribute INIT of FDCE : component is "0"; attribute BOX_TYPE of FDCE : component is "BLACK_BOX"; attribute RLOC of I_36_35 : label is "X0Y0"; begin Q <= Q_DUMMY; I_36_32 : XOR2 port map (I0=>T, I1=>Q_DUMMY, O=>TQ); I_36_35 : FDCE port map (C=>C, CE=>CE, CLR=>CLR, D=>TQ, Q=>Q_DUMMY); end BEHAVIORAL; library ieee; use ieee.std_logic_1164.ALL; use ieee.numeric_std.ALL; library UNISIM; use UNISIM.Vcomponents.ALL; entity CB2CE_MXILINX_GTEXT_LCD320 is port ( C : in std_logic; CE : in std_logic; CLR : in std_logic; CEO : out std_logic; Q0 : out std_logic; Q1 : out std_logic; TC : out std_logic); end CB2CE_MXILINX_GTEXT_LCD320; architecture BEHAVIORAL of CB2CE_MXILINX_GTEXT_LCD320 is attribute HU_SET : string ; attribute BOX_TYPE : string ; signal XLXN_1 : std_logic; signal Q0_DUMMY : std_logic; signal Q1_DUMMY : std_logic; signal TC_DUMMY : std_logic; component FTCE_MXILINX_GTEXT_LCD320 port ( C : in std_logic; CE : in std_logic; CLR : in std_logic; T : in std_logic; Q : out std_logic); end component; component AND2 port ( I0 : in std_logic; I1 : in std_logic; O : out std_logic); end component; attribute BOX_TYPE of AND2 : component is "BLACK_BOX"; component VCC port ( P : out std_logic); end component; attribute BOX_TYPE of VCC : component is "BLACK_BOX"; attribute HU_SET of I_Q0 : label is "I_Q0_0"; attribute HU_SET of I_Q1 : label is "I_Q1_1"; begin Q0 <= Q0_DUMMY; Q1 <= Q1_DUMMY; TC <= TC_DUMMY; I_Q0 : FTCE_MXILINX_GTEXT_LCD320 port map (C=>C, CE=>CE, CLR=>CLR, T=>XLXN_1, Q=>Q0_DUMMY); I_Q1 : FTCE_MXILINX_GTEXT_LCD320 port map (C=>C, CE=>CE, CLR=>CLR, T=>Q0_DUMMY, Q=>Q1_DUMMY); I_36_37 : AND2 port map (I0=>Q1_DUMMY, I1=>Q0_DUMMY, O=>TC_DUMMY); I_36_47 : VCC port map (P=>XLXN_1); I_36_52 : AND2 port map (I0=>CE, I1=>TC_DUMMY, O=>CEO); end BEHAVIORAL; library ieee; use ieee.std_logic_1164.ALL; use ieee.numeric_std.ALL; library UNISIM; use UNISIM.Vcomponents.ALL; entity GTEXT_LCD320 is port ( ADR : in std_logic_vector (11 downto 0); DATA : in std_logic_vector (7 downto 0); GCMD_WR : in std_logic; RESET : in std_logic; SYSCLK50 : in std_logic; TCMD_WR : in std_logic; TXT_WR : in std_logic; BLINK : out std_logic; GDONE : out std_logic; LCDCLK : out std_logic; LCDDATA : out std_logic_vector (3 downto 0); LCDFRAME : out std_logic; LCDLOAD : out std_logic; LCDON : out std_logic; PLOTSYNC : out std_logic; VS_60Hz : out std_logic); end GTEXT_LCD320; architecture BEHAVIORAL of GTEXT_LCD320 is attribute BOX_TYPE : string ; attribute HU_SET : string ; signal CURS_X : std_logic_vector (7 downto 0); signal CURS_Y : std_logic_vector (7 downto 0); signal frame_color : std_logic_vector (3 downto 0); signal graph_color : std_logic_vector (3 downto 0); signal GRID_X : std_logic_vector (7 downto 0); signal GRID_Y : std_logic_vector (7 downto 0); signal pixel_column : std_logic_vector (8 downto 0); signal pixel_line : std_logic_vector (7 downto 0); signal SIZE_X : std_logic_vector (7 downto 0); signal SIZE_Y : std_logic_vector (7 downto 0); signal START_X : std_logic_vector (7 downto 0); signal START_Y : std_logic_vector (7 downto 0); signal text_data : std_logic_vector (15 downto 0); signal TXT_COLOR : std_logic_vector (3 downto 0); signal TXT_DATA16 : std_logic_vector (15 downto 0); signal write_addr : std_logic_vector (15 downto 0); signal XLXN_2113 : std_logic; signal XLXN_2114 : std_logic; signal XLXN_2115 : std_logic; signal XLXN_2117 : std_logic; signal XLXN_2238 : std_logic_vector (3 downto 0); signal XLXN_2266 : std_logic_vector (7 downto 0); signal XLXN_2267 : std_logic_vector (11 downto 0); signal XLXN_2270 : std_logic_vector (9 downto 0); signal XLXN_2355 : std_logic_vector (0 downto 0); signal XLXN_2359 : std_logic; signal XLXN_2360 : std_logic_vector (7 downto 0); signal XLXN_2361 : std_logic_vector (7 downto 0); signal XLXN_2362 : std_logic_vector (7 downto 0); signal XLXN_2363 : std_logic_vector (7 downto 0); signal XLXN_2364 : std_logic; signal XLXN_2398 : std_logic_vector (15 downto 0); signal XLXN_2400 : std_logic; signal XLXN_2407 : std_logic_vector (0 downto 0); signal XLXN_2408 : std_logic; signal XLXN_2409 : std_logic; signal XLXN_2410 : std_logic; signal XLXN_2411 : std_logic; signal XLXN_2413 : std_logic; signal XLXN_2414 : std_logic_vector (0 downto 0); signal XLXN_2420 : std_logic; signal XLXN_2423 : std_logic; signal XLXN_2425 : std_logic; signal XLXI_1144_CLR_openSignal : std_logic; component BUF port ( I : in std_logic; O : out std_logic); end component; attribute BOX_TYPE of BUF : component is "BLACK_BOX"; component mem_font port ( addra : in std_logic_vector (11 downto 0); clka : in std_logic; douta : out std_logic_vector (7 downto 0)); end component; component lcd_timing port ( SYSCLK50 : in std_logic; text_inverse : in std_logic; text_bright : in std_logic; text_dim : in std_logic; text_blink : in std_logic; pixel_bright : in std_logic; pixel_dim : in std_logic; font_data : in std_logic_vector (7 downto 0); text_data : in std_logic_vector (7 downto 0); cursx : in std_logic_vector (7 downto 0); cursy : in std_logic_vector (7 downto 0); lcd_clk : out std_logic; lcd_load : out std_logic; lcd_frame : out std_logic; lcd_on : out std_logic; blink_out : out std_logic; pixel_clk : out std_logic; lcd_addr : out std_logic_vector (14 downto 0); text_addr : out std_logic_vector (9 downto 0); pixel_column : out std_logic_vector (8 downto 0); pixel_line : out std_logic_vector (7 downto 0); font_addr : out std_logic_vector (11 downto 0); lcd_data : out std_logic_vector (3 downto 0); vs60Hz_out : out std_logic); end component; component mem_text_lcd port ( addra : in std_logic_vector (9 downto 0); dina : in std_logic_vector (15 downto 0); wea : in std_logic_vector (0 downto 0); clka : in std_logic; addrb : in std_logic_vector (9 downto 0); clkb : in std_logic; doutb : out std_logic_vector (15 downto 0)); end component; component graph_mem_lcd port ( addra : in std_logic_vector (15 downto 0); dina : in std_logic_vector (0 downto 0); wea : in std_logic_vector (0 downto 0); clka : in std_logic; addrb : in std_logic_vector (15 downto 0); doutb : out std_logic_vector (0 downto 0); clkb : in std_logic); end component; component mid_point port ( clk : in std_logic; reset : in std_logic; XY_wr : in std_logic; X1 : in std_logic_vector (7 downto 0); Y1 : in std_logic_vector (7 downto 0); X2 : in std_logic_vector (7 downto 0); Y2 : in std_logic_vector (7 downto 0); RAM_wr : out std_logic; Done : out std_logic; X_addr : out std_logic_vector (7 downto 0); Y_addr : out std_logic_vector (7 downto 0)); end component; component framer_lcd port ( clk : in std_logic; checker_grid : in std_logic; pixel_clk : in std_logic; pixel_column : in std_logic_vector (8 downto 0); pixel_line : in std_logic_vector (7 downto 0); grid_X : in std_logic_vector (7 downto 0); grid_Y : in std_logic_vector (7 downto 0); start_X : in std_logic_vector (7 downto 0); start_Y : in std_logic_vector (7 downto 0); size_X : in std_logic_vector (7 downto 0); size_Y : in std_logic_vector (7 downto 0); grid : out std_logic; frame : out std_logic; pixel_addr : out std_logic_vector (15 downto 0); plotsync : out std_logic); end component; component AND2 port ( I0 : in std_logic; I1 : in std_logic; O : out std_logic); end component; attribute BOX_TYPE of AND2 : component is "BLACK_BOX"; component OR2 port ( I0 : in std_logic; I1 : in std_logic; O : out std_logic); end component; attribute BOX_TYPE of OR2 : component is "BLACK_BOX"; component parser port ( clk : in std_logic; reset : in std_logic; GCMD_WR : in std_logic; TCMD_WR : in std_logic; plot_done : in std_logic; CMD : in std_logic_vector (3 downto 0); DATA : in std_logic_vector (7 downto 0); XY_wr : out std_logic; GDONE : out std_logic; GSMALL : out std_logic; X1 : out std_logic_vector (7 downto 0); Y1 : out std_logic_vector (7 downto 0); X2 : out std_logic_vector (7 downto 0); Y2 : out std_logic_vector (7 downto 0); FRAMECOLOR : out std_logic_vector (3 downto 0); GRAPHCOLOR : out std_logic_vector (3 downto 0); TEXTCOLOR : out std_logic_vector (3 downto 0); CURSX : out std_logic_vector (7 downto 0); CURSY : out std_logic_vector (7 downto 0); GSTARTX : out std_logic_vector (7 downto 0); GSTARTY : out std_logic_vector (7 downto 0); GSIZEX : out std_logic_vector (7 downto 0); GSIZEY : out std_logic_vector (7 downto 0); GRIDX : out std_logic_vector (7 downto 0); GRIDY : out std_logic_vector (7 downto 0)); end component; component AND3B1 port ( I0 : in std_logic; I1 : in std_logic; I2 : in std_logic; O : out std_logic); end component; attribute BOX_TYPE of AND3B1 : component is "BLACK_BOX"; component CB2CE_MXILINX_GTEXT_LCD320 port ( C : in std_logic; CE : in std_logic; CLR : in std_logic; CEO : out std_logic; Q0 : out std_logic; Q1 : out std_logic; TC : out std_logic); end component; component VCC port ( P : out std_logic); end component; attribute BOX_TYPE of VCC : component is "BLACK_BOX"; attribute HU_SET of XLXI_1144 : label is "XLXI_1144_2"; begin XLXI_1053_0 : BUF port map (I=>XLXN_2238(0), O=>LCDDATA(0)); XLXI_1053_1 : BUF port map (I=>XLXN_2238(1), O=>LCDDATA(1)); XLXI_1053_2 : BUF port map (I=>XLXN_2238(2), O=>LCDDATA(2)); XLXI_1053_3 : BUF port map (I=>XLXN_2238(3), O=>LCDDATA(3)); XLXI_1055 : BUF port map (I=>XLXN_2113, O=>LCDCLK); XLXI_1056 : BUF port map (I=>XLXN_2114, O=>LCDLOAD); XLXI_1057 : BUF port map (I=>XLXN_2115, O=>LCDFRAME); XLXI_1064 : BUF port map (I=>XLXN_2117, O=>LCDON); XLXI_1065 : mem_font port map (addra(11 downto 0)=>XLXN_2267(11 downto 0), clka=>SYSCLK50, douta(7 downto 0)=>XLXN_2266(7 downto 0)); XLXI_1086 : lcd_timing port map (cursx(7 downto 0)=>CURS_X(7 downto 0), cursy(7 downto 0)=>CURS_Y(7 downto 0), font_data(7 downto 0)=>XLXN_2266(7 downto 0), pixel_bright=>XLXN_2413, pixel_dim=>XLXN_2411, SYSCLK50=>SYSCLK50, text_blink=>text_data(10), text_bright=>text_data(9), text_data(7 downto 0)=>text_data(7 downto 0), text_dim=>text_data(8), text_inverse=>text_data(11), blink_out=>BLINK, font_addr(11 downto 0)=>XLXN_2267(11 downto 0), lcd_addr=>open, lcd_clk=>XLXN_2113, lcd_data(3 downto 0)=>XLXN_2238(3 downto 0), lcd_frame=>XLXN_2115, lcd_load=>XLXN_2114, lcd_on=>XLXN_2117, pixel_clk=>XLXN_2400, pixel_column(8 downto 0)=>pixel_column(8 downto 0), pixel_line(7 downto 0)=>pixel_line(7 downto 0), text_addr(9 downto 0)=>XLXN_2270(9 downto 0), vs60Hz_out=>VS_60Hz); XLXI_1098 : mem_text_lcd port map (addra(9 downto 0)=>ADR(9 downto 0), addrb(9 downto 0)=>XLXN_2270(9 downto 0), clka=>SYSCLK50, clkb=>SYSCLK50, dina(15 downto 0)=>TXT_DATA16(15 downto 0), wea(0)=>TXT_WR, doutb(15 downto 0)=>text_data(15 downto 0)); XLXI_1099_0 : BUF port map (I=>DATA(0), O=>TXT_DATA16(0)); XLXI_1099_1 : BUF port map (I=>DATA(1), O=>TXT_DATA16(1)); XLXI_1099_2 : BUF port map (I=>DATA(2), O=>TXT_DATA16(2)); XLXI_1099_3 : BUF port map (I=>DATA(3), O=>TXT_DATA16(3)); XLXI_1099_4 : BUF port map (I=>DATA(4), O=>TXT_DATA16(4)); XLXI_1099_5 : BUF port map (I=>DATA(5), O=>TXT_DATA16(5)); XLXI_1099_6 : BUF port map (I=>DATA(6), O=>TXT_DATA16(6)); XLXI_1099_7 : BUF port map (I=>DATA(7), O=>TXT_DATA16(7)); XLXI_1100_0 : BUF port map (I=>TXT_COLOR(0), O=>TXT_DATA16(8)); XLXI_1100_1 : BUF port map (I=>TXT_COLOR(1), O=>TXT_DATA16(9)); XLXI_1100_2 : BUF port map (I=>TXT_COLOR(2), O=>TXT_DATA16(10)); XLXI_1100_3 : BUF port map (I=>TXT_COLOR(3), O=>TXT_DATA16(11)); XLXI_1114 : graph_mem_lcd port map (addra(15 downto 0)=>write_addr(15 downto 0), addrb(15 downto 0)=>XLXN_2398(15 downto 0), clka=>SYSCLK50, clkb=>SYSCLK50, dina(0)=>graph_color(1), wea(0)=>XLXN_2355(0), doutb(0)=>XLXN_2414(0)); XLXI_1115 : graph_mem_lcd port map (addra(15 downto 0)=>write_addr(15 downto 0), addrb(15 downto 0)=>XLXN_2398(15 downto 0), clka=>SYSCLK50, clkb=>SYSCLK50, dina(0)=>graph_color(0), wea(0)=>XLXN_2355(0), doutb(0)=>XLXN_2407(0)); XLXI_1117 : mid_point port map (clk=>SYSCLK50, reset=>RESET, XY_wr=>XLXN_2359, X1(7 downto 0)=>XLXN_2362(7 downto 0), X2(7 downto 0)=>XLXN_2360(7 downto 0), Y1(7 downto 0)=>XLXN_2363(7 downto 0), Y2(7 downto 0)=>XLXN_2361(7 downto 0), Done=>XLXN_2364, RAM_wr=>XLXN_2355(0), X_addr(7 downto 0)=>write_addr(7 downto 0), Y_addr(7 downto 0)=>write_addr(15 downto 8)); XLXI_1135 : framer_lcd port map (checker_grid=>frame_color(2), clk=>SYSCLK50, grid_X(7 downto 0)=>GRID_X(7 downto 0), grid_Y(7 downto 0)=>GRID_Y(7 downto 0), pixel_clk=>XLXN_2400, pixel_column(8 downto 0)=>pixel_column(8 downto 0), pixel_line(7 downto 0)=>pixel_line(7 downto 0), size_X(7 downto 0)=>SIZE_X(7 downto 0), size_Y(7 downto 0)=>SIZE_Y(7 downto 0), start_X(7 downto 0)=>START_X(7 downto 0), start_Y(7 downto 0)=>START_Y(7 downto 0), frame=>XLXN_2410, grid=>XLXN_2420, pixel_addr(15 downto 0)=>XLXN_2398(15 downto 0), plotsync=>XLXN_2423); XLXI_1138 : AND2 port map (I0=>XLXN_2410, I1=>XLXN_2408, O=>XLXN_2411); XLXI_1139 : OR2 port map (I0=>XLXN_2409, I1=>XLXN_2407(0), O=>XLXN_2408); XLXI_1140 : AND2 port map (I0=>XLXN_2410, I1=>XLXN_2414(0), O=>XLXN_2413); XLXI_1141 : parser port map (clk=>SYSCLK50, CMD(3 downto 0)=>ADR(3 downto 0), DATA(7 downto 0)=>DATA(7 downto 0), GCMD_WR=>GCMD_WR, plot_done=>XLXN_2364, reset=>RESET, TCMD_WR=>TCMD_WR, CURSX(7 downto 0)=>CURS_X(7 downto 0), CURSY(7 downto 0)=>CURS_Y(7 downto 0), FRAMECOLOR(3 downto 0)=>frame_color(3 downto 0), GDONE=>GDONE, GRAPHCOLOR(3 downto 0)=>graph_color(3 downto 0), GRIDX(7 downto 0)=>GRID_X(7 downto 0), GRIDY(7 downto 0)=>GRID_Y(7 downto 0), GSIZEX(7 downto 0)=>SIZE_X(7 downto 0), GSIZEY(7 downto 0)=>SIZE_Y(7 downto 0), GSMALL=>open, GSTARTX(7 downto 0)=>START_X(7 downto 0), GSTARTY(7 downto 0)=>START_Y(7 downto 0), TEXTCOLOR(3 downto 0)=>TXT_COLOR(3 downto 0), XY_wr=>XLXN_2359, X1(7 downto 0)=>XLXN_2362(7 downto 0), X2(7 downto 0)=>XLXN_2360(7 downto 0), Y1(7 downto 0)=>XLXN_2363(7 downto 0), Y2(7 downto 0)=>XLXN_2361(7 downto 0)); XLXI_1143 : AND3B1 port map (I0=>XLXN_2414(0), I1=>frame_color(3), I2=>XLXN_2420, O=>XLXN_2409); XLXI_1144 : CB2CE_MXILINX_GTEXT_LCD320 port map (C=>XLXN_2423, CE=>XLXN_2425, CLR=>XLXI_1144_CLR_openSignal, CEO=>open, Q0=>PLOTSYNC, Q1=>open, TC=>open); XLXI_1146 : VCC port map (P=>XLXN_2425); end BEHAVIORAL;