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-- Copyright (c) 1995-2008 Xilinx, Inc.  All rights reserved.
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--   ____  ____ 
--  /   /\/   / 
-- /___/  \  /    Vendor: Xilinx 
-- \   \   \/     Version : 10.1.03
--  \   \         Application : sch2vhdl
--  /   /         Filename : UART.vhf
-- /___/   /\     Timestamp : 11/03/2009 12:44:16
-- \   \  /  \ 
--  \___\/\___\ 
--
--Command: C:\Xilinx\10.1\ISE\bin\nt\unwrapped\sch2vhdl.exe -intstyle ise -family spartan3 -flat -suppress -w E:/ProjFPGA/ct-BASIC-LCD/source/UART.sch UART.vhf
--Design Name: UART
--Device: spartan3
--Purpose:
--    This vhdl netlist is translated from an ECS schematic. It can be 
--    synthesis and simulted, but it should not be modified. 
--

library ieee;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.ALL;
library UNISIM;
use UNISIM.Vcomponents.ALL;

entity UART is
   port ( BaudSel  : in    std_logic_vector (2 downto 0); 
          RxD      : in    std_logic; 
          Rx_ack   : in    std_logic; 
          Rx_flush : in    std_logic; 
          SYSCLK   : in    std_logic; 
          Tx_Data  : in    std_logic_vector (7 downto 0); 
          Tx_reset : in    std_logic; 
          Tx_write : in    std_logic; 
          Rx_Data  : out   std_logic_vector (7 downto 0); 
          Rx_full  : out   std_logic; 
          Rx_valid : out   std_logic; 
          TxD      : out   std_logic; 
          Tx_full  : out   std_logic);
end UART;

architecture BEHAVIORAL of UART is
   attribute INIT       : string ;
   attribute BOX_TYPE   : string ;
   signal XLXN_32  : std_logic;
   signal XLXN_57  : std_logic;
   signal XLXN_58  : std_logic;
   signal XLXN_59  : std_logic;
   signal XLXN_66  : std_logic;
   component kcbaud
      port ( SYSCLK  : in    std_logic; 
             BAUDx16 : out   std_logic; 
             BaudSel : in    std_logic_vector (2 downto 0));
   end component;
   
   component uart_rx
      port ( serial_in           : in    std_logic; 
             read_buffer         : in    std_logic; 
             reset_buffer        : in    std_logic; 
             en_16_x_baud        : in    std_logic; 
             clk                 : in    std_logic; 
             buffer_data_present : out   std_logic; 
             buffer_full         : out   std_logic; 
             buffer_half_full    : out   std_logic; 
             data_out            : out   std_logic_vector (7 downto 0));
   end component;
   
   component uart_tx
      port ( write_buffer     : in    std_logic; 
             reset_buffer     : in    std_logic; 
             en_16_x_baud     : in    std_logic; 
             clk              : in    std_logic; 
             data_in          : in    std_logic_vector (7 downto 0); 
             serial_out       : out   std_logic; 
             buffer_full      : out   std_logic; 
             buffer_half_full : out   std_logic);
   end component;
   
   component FD
      -- synopsys translate_off
      generic( INIT : bit :=  '0');
      -- synopsys translate_on
      port ( C : in    std_logic; 
             D : in    std_logic; 
             Q : out   std_logic);
   end component;
   attribute INIT of FD : component is "0";
   attribute BOX_TYPE of FD : component is "BLACK_BOX";
   
   component AND2B1
      port ( I0 : in    std_logic; 
             I1 : in    std_logic; 
             O  : out   std_logic);
   end component;
   attribute BOX_TYPE of AND2B1 : component is "BLACK_BOX";
   
begin
   XLXI_6 : kcbaud
      port map (BaudSel(2 downto 0)=>BaudSel(2 downto 0),
                SYSCLK=>SYSCLK,
                BAUDx16=>XLXN_32);
   
   XLXI_8 : uart_rx
      port map (clk=>SYSCLK,
                en_16_x_baud=>XLXN_32,
                read_buffer=>XLXN_58,
                reset_buffer=>Rx_flush,
                serial_in=>RxD,
                buffer_data_present=>Rx_valid,
                buffer_full=>open,
                buffer_half_full=>Rx_full,
                data_out(7 downto 0)=>Rx_Data(7 downto 0));
   
   XLXI_9 : uart_tx
      port map (clk=>SYSCLK,
                data_in(7 downto 0)=>Tx_Data(7 downto 0),
                en_16_x_baud=>XLXN_32,
                reset_buffer=>Tx_reset,
                write_buffer=>XLXN_66,
                buffer_full=>Tx_full,
                buffer_half_full=>open,
                serial_out=>TxD);
   
   XLXI_10 : FD
      port map (C=>SYSCLK,
                D=>Rx_ack,
                Q=>XLXN_57);
   
   XLXI_11 : AND2B1
      port map (I0=>XLXN_57,
                I1=>Rx_ack,
                O=>XLXN_58);
   
   XLXI_12 : FD
      port map (C=>SYSCLK,
                D=>Tx_write,
                Q=>XLXN_59);
   
   XLXI_13 : AND2B1
      port map (I0=>XLXN_59,
                I1=>Tx_write,
                O=>XLXN_66);
   
end BEHAVIORAL;