Logical network XLXI_1000/XLXI_1144/CEO has no load. The above warning message base_net_load_rule is repeated 171 more times for the following (max. 5 shown): XLXI_980/XLXI_539/XLXI_119/Q<0>, XLXI_980/XLXI_539/XLXI_119/Q<10>, XLXI_980/XLXI_539/XLXI_119/Q<11>, XLXI_980/XLXI_539/XLXI_119/Q<12>, XLXI_980/XLXI_539/XLXI_119/Q<13> To see the details of these warning messages, please use the -detail switch. No environment variables are currently set. The following XORCY(s) is/are demoted to LUTs because there is no MUXCY associated with them. Therefore, we cannot recognize the standard carry chain structure: XORCY symbol "XLXI_1000/XLXI_1086/Mcount_pixelblock_count_xor<0>" (output signal=XLXI_1000/XLXI_1086/Result<0>5) All of the single ended outputs in this design are using slew rate limited output drivers. The delay on speed critical single ended outputs can be dramatically reduced by designating them as fast outputs. Clock buffer is designated to drive clock loads. BUFGMUX symbol "physical_group_XLXI_980/LC128/XLXI_980/XLXI_525/D0_BUFG" (output signal=XLXI_980/LC128) has a mix of clock and non-clock loads. The non-clock loads are: Pin D of XLXI_980/XLXI_539/XLXI_131 The function generator XLXI_1011/cpu/alu/Q_t_mux0000<1>216 failed to merge with F5 multiplexer XLXI_1011/cpu/P_1_mux0000505. There is a conflict for the FXMUX. The design will exhibit suboptimal timing. The function generator XLXI_1011/cpu/Set_Addr_To_r_mux0001<0>175 failed to merge with F5 multiplexer XLXI_1011/cpu/Set_Addr_To_r_mux0001<0>176_f5. There is a conflict for the FXMUX. The design will exhibit suboptimal timing. The function generator XLXI_1011/cpu/mcode/Mmux_Jump_mux0015_3 failed to merge with F5 multiplexer XLXI_1011/cpu/mcode/Mmux_Jump_mux0014_2_f5. There is a conflict for the FXMUX. The design will exhibit suboptimal timing. Gated clock. Clock net XLXI_984/Mult_in1_12_not0001 is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop. Gated clock. Clock net XLXN_1732 is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop. Gated clock. Clock net XLXI_984/CPU_DATAo_cmp_eq0000 is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop. Gated clock. Clock net XLXI_984/CPU_DATAo_not0005 is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop. Gated clock. Clock net XLXI_980/XLXN_1105 is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop. Gated clock. Clock net XLXI_984/CPU_DATAo_not0006 is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop. Gated clock. Clock net XLXI_984/CPU_DATAo_not0009 is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop. Gated clock. Clock net XLXI_984/RAM_ADR_16_not0001 is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop. Gated clock. Clock net XLXI_984/CPU_DATAo_not0007 is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop. Gated clock. Clock net XLXI_984/CPU_DATAo_not0008 is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop. Gated clock. Clock net XLXI_980/XLXN_1103 is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop.