No user timing constraints were detected or you have set the option to ignore timing constraints ("par -x"). Place and Route will run in "Performance Evaluation Mode" to automatically improve the performance of all internal clocks in this design. The PAR timing summary will list the performance achieved for each clock. Note: For the fastest runtime, set the effort level to "std". For best performance, set the effort level to "high". For a balance between the fastest runtime and best performance, set the effort level to "med". The input design contains local clock signal(s). To get a better result, we recommend users run map with the "-timing" option set before starting the placement. A clock IOB / clock component pair have been found that are not placed at an optimal clock IOB / clock site pair. The clock component <F_SCK_BUFGP/BUFG> is placed at site <BUFGMUX1>. The IO component <F_SCK> is placed at site <P70>. This will not allow the use of the fast path between the IO and the Clock buffer. This is normally an ERROR but the CLOCK_DEDICATED_ROUTE constraint was applied on COMP.PIN <F_SCK.PAD> allowing your design to continue. This constraint disables all clock placer rules related to the specified COMP.PIN. The use of this override is highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in the design. N/A entries in the Constraints list may indicate that the constraint does not cover any paths or that it has no requested value. CLK Net:XLXI_984/CPU_DATAo_not0007 is being routed on general routing resources. If you are trying to use local clocking techniques, evaluate the placement of the clock's source and loads to ensure it meets the guidelines for local clocking. Otherwise, consider placing this clock on a dedicated clock routing resource. For more information on clock routing resources, see the target architecture's user guide. CLK Net:XLXI_1000/XLXI_1086/frame_intern is being routed on general routing resources. If you are trying to use local clocking techniques, evaluate the placement of the clock's source and loads to ensure it meets the guidelines for local clocking. Otherwise, consider placing this clock on a dedicated clock routing resource. For more information on clock routing resources, see the target architecture's user guide. CLK Net:XLXI_1011/ena_count<1> may have excessive skew because 1 CLK pins and 16 NON_CLK pins failed to route using a CLK template. CLK Net:XLXI_1000/XLXI_1135/yvalid may have excessive skew because 1 CLK pins and 8 NON_CLK pins failed to route using a CLK template. N/A entries in the Constraints list may indicate that the constraint does not cover any paths or that it has no requested value.