--------------------------------------------------------------------------------
-- Copyright (c) 1995-2003 Xilinx, Inc.
-- All Right Reserved.
--------------------------------------------------------------------------------
--   ____  ____ 
--  /   /\/   / 
-- /___/  \  /    Vendor: Xilinx 
-- \   \   \/     Version : 10.1.03
--  \   \         Application : ISE
--  /   /         Filename : bresenham_test.ant
-- /___/   /\     Timestamp : Sun May 17 13:11:43 2009
-- \   \  /  \ 
--  \___\/\___\ 
--
--Command: 
--Design Name: bresenham_test
--Device: Xilinx
--

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
USE IEEE.STD_LOGIC_TEXTIO.ALL;
USE STD.TEXTIO.ALL;

ENTITY bresenham_test IS
END bresenham_test;

ARCHITECTURE testbench_arch OF bresenham_test IS
    FILE RESULTS: TEXT OPEN WRITE_MODE IS "E:\ProjFPGA\ct-BASIC\main\bresenham_test.ano";

    COMPONENT mid_point
        PORT (
            clk : In std_logic;
            reset : In std_logic;
            X1 : In std_logic_vector (7 DownTo 0);
            Y1 : In std_logic_vector (7 DownTo 0);
            X2 : In std_logic_vector (7 DownTo 0);
            Y2 : In std_logic_vector (7 DownTo 0);
            XY_wr : In std_logic;
            RAM_wr : Out std_logic;
            Done : Out std_logic;
            X_addr : Out std_logic_vector (7 DownTo 0);
            Y_addr : Out std_logic_vector (7 DownTo 0)
        );
    END COMPONENT;

    SIGNAL clk : std_logic := '0';
    SIGNAL reset : std_logic := '0';
    SIGNAL X1 : std_logic_vector (7 DownTo 0) := "00000000";
    SIGNAL Y1 : std_logic_vector (7 DownTo 0) := "00000000";
    SIGNAL X2 : std_logic_vector (7 DownTo 0) := "00000000";
    SIGNAL Y2 : std_logic_vector (7 DownTo 0) := "00000000";
    SIGNAL XY_wr : std_logic := '0';
    SIGNAL RAM_wr : std_logic := '0';
    SIGNAL Done : std_logic := '0';
    SIGNAL X_addr : std_logic_vector (7 DownTo 0) := "00000000";
    SIGNAL Y_addr : std_logic_vector (7 DownTo 0) := "00000000";

    SHARED VARIABLE TX_ERROR : INTEGER := 0;
    SHARED VARIABLE TX_OUT : LINE;

    constant PERIOD : time := 200 ns;
    constant DUTY_CYCLE : real := 0.5;
    constant OFFSET : time := 100 ns;

    BEGIN
        UUT : mid_point
        PORT MAP (
            clk => clk,
            reset => reset,
            X1 => X1,
            Y1 => Y1,
            X2 => X2,
            Y2 => Y2,
            XY_wr => XY_wr,
            RAM_wr => RAM_wr,
            Done => Done,
            X_addr => X_addr,
            Y_addr => Y_addr
        );

        PROCESS    -- clock process for clk
        BEGIN
            WAIT for OFFSET;
            CLOCK_LOOP : LOOP
                clk <= '0';
                WAIT FOR (PERIOD - (PERIOD * DUTY_CYCLE));
                clk <= '1';
                WAIT FOR (PERIOD * DUTY_CYCLE);
            END LOOP CLOCK_LOOP;
        END PROCESS;

        PROCESS    -- Annotation process for clk
            VARIABLE TX_TIME : INTEGER := 0;

            PROCEDURE ANNOTATE_RAM_wr(
                TX_TIME : INTEGER
            ) IS
                VARIABLE TX_STR : String(1 to 4096);
                VARIABLE TX_LOC : LINE;
            BEGIN
                STD.TEXTIO.write(TX_LOC, string'("Annotate["));
                STD.TEXTIO.write(TX_LOC, TX_TIME);
                STD.TEXTIO.write(TX_LOC, string'(", RAM_wr, "));
                IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, RAM_wr);
                STD.TEXTIO.write(TX_LOC, string'("]"));
                TX_STR(TX_LOC.all'range) := TX_LOC.all;
                STD.TEXTIO.writeline(RESULTS, TX_LOC);
                STD.TEXTIO.Deallocate(TX_LOC);
            END;
            PROCEDURE ANNOTATE_Done(
                TX_TIME : INTEGER
            ) IS
                VARIABLE TX_STR : String(1 to 4096);
                VARIABLE TX_LOC : LINE;
            BEGIN
                STD.TEXTIO.write(TX_LOC, string'("Annotate["));
                STD.TEXTIO.write(TX_LOC, TX_TIME);
                STD.TEXTIO.write(TX_LOC, string'(", Done, "));
                IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, Done);
                STD.TEXTIO.write(TX_LOC, string'("]"));
                TX_STR(TX_LOC.all'range) := TX_LOC.all;
                STD.TEXTIO.writeline(RESULTS, TX_LOC);
                STD.TEXTIO.Deallocate(TX_LOC);
            END;
            PROCEDURE ANNOTATE_X_addr(
                TX_TIME : INTEGER
            ) IS
                VARIABLE TX_STR : String(1 to 4096);
                VARIABLE TX_LOC : LINE;
            BEGIN
                STD.TEXTIO.write(TX_LOC, string'("Annotate["));
                STD.TEXTIO.write(TX_LOC, TX_TIME);
                STD.TEXTIO.write(TX_LOC, string'(", X_addr, "));
                IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, X_addr);
                STD.TEXTIO.write(TX_LOC, string'("]"));
                TX_STR(TX_LOC.all'range) := TX_LOC.all;
                STD.TEXTIO.writeline(RESULTS, TX_LOC);
                STD.TEXTIO.Deallocate(TX_LOC);
            END;
            PROCEDURE ANNOTATE_Y_addr(
                TX_TIME : INTEGER
            ) IS
                VARIABLE TX_STR : String(1 to 4096);
                VARIABLE TX_LOC : LINE;
            BEGIN
                STD.TEXTIO.write(TX_LOC, string'("Annotate["));
                STD.TEXTIO.write(TX_LOC, TX_TIME);
                STD.TEXTIO.write(TX_LOC, string'(", Y_addr, "));
                IEEE.STD_LOGIC_TEXTIO.write(TX_LOC, Y_addr);
                STD.TEXTIO.write(TX_LOC, string'("]"));
                TX_STR(TX_LOC.all'range) := TX_LOC.all;
                STD.TEXTIO.writeline(RESULTS, TX_LOC);
                STD.TEXTIO.Deallocate(TX_LOC);
            END;
        BEGIN
            WAIT for 1 fs;
            ANNOTATE_RAM_wr(0);
            ANNOTATE_Done(0);
            ANNOTATE_X_addr(0);
            ANNOTATE_Y_addr(0);
            WAIT for OFFSET;
            TX_TIME := TX_TIME + 100;
            ANNO_LOOP : LOOP
                --Rising Edge
                WAIT for 115 ns;
                TX_TIME := TX_TIME + 115;
                ANNOTATE_RAM_wr(TX_TIME);
                ANNOTATE_Done(TX_TIME);
                ANNOTATE_X_addr(TX_TIME);
                ANNOTATE_Y_addr(TX_TIME);
                WAIT for 85 ns;
                TX_TIME := TX_TIME + 85;
            END LOOP ANNO_LOOP;
        END PROCESS;

        PROCESS
            BEGIN
                -- -------------  Current Time:  185ns
                WAIT FOR 185 ns;
                reset <= '1';
                -- -------------------------------------
                -- -------------  Current Time:  385ns
                WAIT FOR 200 ns;
                reset <= '0';
                -- -------------------------------------
                -- -------------  Current Time:  1185ns
                WAIT FOR 800 ns;
                X1 <= "00000100";
                Y2 <= "00001000";
                -- -------------------------------------
                -- -------------  Current Time:  1385ns
                WAIT FOR 200 ns;
                Y1 <= "00000100";
                X2 <= "00001000";
                -- -------------------------------------
                -- -------------  Current Time:  2985ns
                WAIT FOR 1600 ns;
                XY_wr <= '1';
                -- -------------------------------------
                -- -------------  Current Time:  3185ns
                WAIT FOR 200 ns;
                XY_wr <= '0';
                -- -------------------------------------
                WAIT FOR 17015 ns;

                STD.TEXTIO.write(TX_OUT, string'("Total[]"));
                STD.TEXTIO.writeline(RESULTS, TX_OUT);
                ASSERT (FALSE) REPORT
                    "Success! Simulation for annotation completed"
                    SEVERITY FAILURE;
            END PROCESS;

    END testbench_arch;