WARNING:PhysDesignRules:372 - Gated clock. Clock net
   XLXI_984/Mult_in1_12_not0001 is sourced by a combinatorial pin. This is not
   good design practice. Use the CE pin to control the loading of data into the
   flip-flop.
WARNING:PhysDesignRules:372 - Gated clock. Clock net XLXN_1732 is sourced by a
   combinatorial pin. This is not good design practice. Use the CE pin to
   control the loading of data into the flip-flop.
WARNING:PhysDesignRules:372 - Gated clock. Clock net
   XLXI_984/CPU_DATAo_cmp_eq0000 is sourced by a combinatorial pin. This is not
   good design practice. Use the CE pin to control the loading of data into the
   flip-flop.
WARNING:PhysDesignRules:372 - Gated clock. Clock net XLXI_984/CPU_DATAo_not0005
   is sourced by a combinatorial pin. This is not good design practice. Use the
   CE pin to control the loading of data into the flip-flop.
WARNING:PhysDesignRules:372 - Gated clock. Clock net XLXI_980/XLXN_1105 is
   sourced by a combinatorial pin. This is not good design practice. Use the CE
   pin to control the loading of data into the flip-flop.
WARNING:PhysDesignRules:372 - Gated clock. Clock net XLXI_984/CPU_DATAo_not0006
   is sourced by a combinatorial pin. This is not good design practice. Use the
   CE pin to control the loading of data into the flip-flop.
WARNING:PhysDesignRules:372 - Gated clock. Clock net XLXI_984/CPU_DATAo_not0009
   is sourced by a combinatorial pin. This is not good design practice. Use the
   CE pin to control the loading of data into the flip-flop.
WARNING:PhysDesignRules:372 - Gated clock. Clock net XLXI_984/RAM_ADR_16_not0001
   is sourced by a combinatorial pin. This is not good design practice. Use the
   CE pin to control the loading of data into the flip-flop.
WARNING:PhysDesignRules:372 - Gated clock. Clock net XLXI_984/CPU_DATAo_not0007
   is sourced by a combinatorial pin. This is not good design practice. Use the
   CE pin to control the loading of data into the flip-flop.
WARNING:PhysDesignRules:372 - Gated clock. Clock net XLXI_984/CPU_DATAo_not0008
   is sourced by a combinatorial pin. This is not good design practice. Use the
   CE pin to control the loading of data into the flip-flop.
WARNING:PhysDesignRules:372 - Gated clock. Clock net XLXI_980/XLXN_1103 is
   sourced by a combinatorial pin. This is not good design practice. Use the CE
   pin to control the loading of data into the flip-flop.
DRC detected 0 errors and 11 warnings.  Please see the previously displayed
individual error or warning messages for more details.