Release 10.1.03 Map K.39 (nt)
Xilinx Map Application Log File for Design 'main_test'

Design Information
------------------
Command Line   : map -ise E:/ProjFPGA/ct-BASIC-LCD/main/main.ise -intstyle ise
-p xc3s400-tq144-4 -cm area -pr off -k 4 -c 100 -o main_test_map.ncd
main_test.ngd main_test.pcf 
Target Device  : xc3s400
Target Package : tq144
Target Speed   : -4
Mapper Version : spartan3 -- $Revision: 1.46.12.2 $
Mapped Date    : Mon Jun 29 20:28:01 2009

Mapping design into LUTs...
Running directed packing...
Running delay-based LUT packing...
Running related packing...

Design Summary
--------------

Design Summary:
Number of errors:      0
Number of warnings:    7
Logic Utilization:
  Total Number Slice Registers:         328 out of   7,168    4%
    Number used as Flip Flops:          327
    Number used as Latches:               1
  Number of 4 input LUTs:               463 out of   7,168    6%
Logic Distribution:
  Number of occupied Slices:            328 out of   3,584    9%
    Number of Slices containing only related logic:     328 out of     328 100%
    Number of Slices containing unrelated logic:          0 out of     328   0%
      *See NOTES below for an explanation of the effects of unrelated logic.
  Total Number of 4 input LUTs:         527 out of   7,168    7%
    Number used as logic:               463
    Number used as a route-thru:         64
  Number of bonded IOBs:                 18 out of      97   18%
  Number of RAMB16s:                      9 out of      16   56%
  Number of BUFGMUXs:                     4 out of       8   50%

Peak Memory Usage:  144 MB
Total REAL time to MAP completion:  3 secs 
Total CPU time to MAP completion:   2 secs 

NOTES:

   Related logic is defined as being logic that shares connectivity - e.g. two
   LUTs are "related" if they share common inputs.  When assembling slices,
   Map gives priority to combine logic that is related.  Doing so results in
   the best timing performance.

   Unrelated logic shares no connectivity.  Map will only begin packing
   unrelated logic into a slice once 99% of the slices are occupied through
   related logic packing.

   Note that once logic distribution reaches the 99% level through related
   logic packing, this does not mean the device is completely utilized.
   Unrelated logic packing will then begin, continuing until all usable LUTs
   and FFs are occupied.  Depending on your timing budget, increased levels of
   unrelated logic packing may adversely affect the overall timing performance
   of your design.

Mapping completed.
See MAP report file "main_test_map.mrp" for details.