// The following must be inserted into your Verilog file for this
// core to be instantiated. Change the instance name and port connections
// (in parentheses) to your own signal names.
fifo YourInstanceName (
.din(din), // Bus [7 : 0]
.rd_clk(rd_clk),
.rd_en(rd_en),
.rst(rst),
.wr_clk(wr_clk),
.wr_en(wr_en),
.almost_full(almost_full),
.dout(dout), // Bus [7 : 0]
.empty(empty),
.full(full));
// The following must be inserted into your Verilog file for this
// core to be instantiated. Change the instance name and port connections
// (in parentheses) to your own signal names.
mem_font YourInstanceName (
.clka(clka),
.addra(addra), // Bus [11 : 0]
.douta(douta)); // Bus [7 : 0]
// The following must be inserted into your Verilog file for this
// core to be instantiated. Change the instance name and port connections
// (in parentheses) to your own signal names.
mem_text YourInstanceName (
.clka(clka),
.dina(dina), // Bus [7 : 0]
.addra(addra), // Bus [11 : 0]
.wea(wea), // Bus [0 : 0]
.douta(douta), // Bus [7 : 0]
.clkb(clkb),
.dinb(dinb), // Bus [7 : 0]
.addrb(addrb), // Bus [11 : 0]
.web(web), // Bus [0 : 0]
.doutb(doutb)); // Bus [7 : 0]
// The following must be inserted into your Verilog file for this
// core to be instantiated. Change the instance name and port connections
// (in parentheses) to your own signal names.
key_fifo YourInstanceName (
.din(din), // Bus [7 : 0]
.rd_clk(rd_clk),
.rd_en(rd_en),
.rst(rst),
.wr_clk(wr_clk),
.wr_en(wr_en),
.dout(dout), // Bus [7 : 0]
.empty(empty),
.full(full));
// The following must be inserted into your Verilog file for this
// core to be instantiated. Change the instance name and port connections
// (in parentheses) to your own signal names.
mem_color YourInstanceName (
.addra(addra), // Bus [11 : 0]
.addrb(addrb), // Bus [11 : 0]
.clka(clka),
.clkb(clkb),
.dina(dina), // Bus [3 : 0]
.dinb(dinb), // Bus [3 : 0]
.douta(douta), // Bus [3 : 0]
.doutb(doutb), // Bus [3 : 0]
.wea(wea),
.web(web));
// The following must be inserted into your Verilog file for this
// core to be instantiated. Change the instance name and port connections
// (in parentheses) to your own signal names.
graphcolor_mem YourInstanceName (
.clka(clka),
.dina(dina), // Bus [3 : 0]
.addra(addra), // Bus [13 : 0]
.wea(wea), // Bus [0 : 0]
.clkb(clkb),
.addrb(addrb), // Bus [13 : 0]
.doutb(doutb)); // Bus [3 : 0]
// The following must be inserted into your Verilog file for this
// core to be instantiated. Change the instance name and port connections
// (in parentheses) to your own signal names.
graph_mem YourInstanceName (
.clka(clka),
.dina(dina), // Bus [0 : 0]
.addra(addra), // Bus [15 : 0]
.wea(wea), // Bus [0 : 0]
.clkb(clkb),
.addrb(addrb), // Bus [15 : 0]
.doutb(doutb)); // Bus [0 : 0]
// The following must be inserted into your Verilog file for this
// core to be instantiated. Change the instance name and port connections
// (in parentheses) to your own signal names.
lcd_ram YourInstanceName (
.clka(clka),
.dina(dina), // Bus [3 : 0]
.addra(addra), // Bus [14 : 0]
.wea(wea), // Bus [0 : 0]
.clkb(clkb),
.addrb(addrb), // Bus [14 : 0]
.doutb(doutb)); // Bus [3 : 0]
// The following must be inserted into your Verilog file for this
// core to be instantiated. Change the instance name and port connections
// (in parentheses) to your own signal names.
mem_text_lcd YourInstanceName (
.clka(clka),
.dina(dina), // Bus [15 : 0]
.addra(addra), // Bus [9 : 0]
.wea(wea), // Bus [0 : 0]
.clkb(clkb),
.addrb(addrb), // Bus [9 : 0]
.doutb(doutb)); // Bus [15 : 0]
// The following must be inserted into your Verilog file for this
// core to be instantiated. Change the instance name and port connections
// (in parentheses) to your own signal names.
graph_mem_lcd YourInstanceName (
.clka(clka),
.dina(dina), // Bus [0 : 0]
.addra(addra), // Bus [15 : 0]
.wea(wea), // Bus [0 : 0]
.clkb(clkb),
.addrb(addrb), // Bus [15 : 0]
.doutb(doutb)); // Bus [0 : 0]
-- The following code must appear in the VHDL architecture header:
component fifo
port (
din: IN std_logic_VECTOR(7 downto 0);
rd_clk: IN std_logic;
rd_en: IN std_logic;
rst: IN std_logic;
wr_clk: IN std_logic;
wr_en: IN std_logic;
almost_full: OUT std_logic;
dout: OUT std_logic_VECTOR(7 downto 0);
empty: OUT std_logic;
full: OUT std_logic);
end component;
-------------------------------------------------------------
-- The following code must appear in the VHDL architecture body.
-- Substitute your own instance name and net names.
your_instance_name : fifo
port map (
din => din,
rd_clk => rd_clk,
rd_en => rd_en,
rst => rst,
wr_clk => wr_clk,
wr_en => wr_en,
almost_full => almost_full,
dout => dout,
empty => empty,
full => full);
-- The following code must appear in the VHDL architecture header:
component mem_font
port (
clka: IN std_logic;
addra: IN std_logic_VECTOR(11 downto 0);
douta: OUT std_logic_VECTOR(7 downto 0));
end component;
-------------------------------------------------------------
-- The following code must appear in the VHDL architecture body.
-- Substitute your own instance name and net names.
your_instance_name : mem_font
port map (
clka => clka,
addra => addra,
douta => douta);
-- The following code must appear in the VHDL architecture header:
component mem_text
port (
clka: IN std_logic;
dina: IN std_logic_VECTOR(7 downto 0);
addra: IN std_logic_VECTOR(11 downto 0);
wea: IN std_logic_VECTOR(0 downto 0);
douta: OUT std_logic_VECTOR(7 downto 0);
clkb: IN std_logic;
dinb: IN std_logic_VECTOR(7 downto 0);
addrb: IN std_logic_VECTOR(11 downto 0);
web: IN std_logic_VECTOR(0 downto 0);
doutb: OUT std_logic_VECTOR(7 downto 0));
end component;
-------------------------------------------------------------
-- The following code must appear in the VHDL architecture body.
-- Substitute your own instance name and net names.
your_instance_name : mem_text
port map (
clka => clka,
dina => dina,
addra => addra,
wea => wea,
douta => douta,
clkb => clkb,
dinb => dinb,
addrb => addrb,
web => web,
doutb => doutb);
-- The following code must appear in the VHDL architecture header:
component key_fifo
port (
din: IN std_logic_VECTOR(7 downto 0);
rd_clk: IN std_logic;
rd_en: IN std_logic;
rst: IN std_logic;
wr_clk: IN std_logic;
wr_en: IN std_logic;
dout: OUT std_logic_VECTOR(7 downto 0);
empty: OUT std_logic;
full: OUT std_logic);
end component;
-------------------------------------------------------------
-- The following code must appear in the VHDL architecture body.
-- Substitute your own instance name and net names.
your_instance_name : key_fifo
port map (
din => din,
rd_clk => rd_clk,
rd_en => rd_en,
rst => rst,
wr_clk => wr_clk,
wr_en => wr_en,
dout => dout,
empty => empty,
full => full);
-- The following code must appear in the VHDL architecture header:
component mem_color
port (
addra: IN std_logic_VECTOR(11 downto 0);
addrb: IN std_logic_VECTOR(11 downto 0);
clka: IN std_logic;
clkb: IN std_logic;
dina: IN std_logic_VECTOR(3 downto 0);
dinb: IN std_logic_VECTOR(3 downto 0);
douta: OUT std_logic_VECTOR(3 downto 0);
doutb: OUT std_logic_VECTOR(3 downto 0);
wea: IN std_logic;
web: IN std_logic);
end component;
-------------------------------------------------------------
-- The following code must appear in the VHDL architecture body.
-- Substitute your own instance name and net names.
your_instance_name : mem_color
port map (
addra => addra,
addrb => addrb,
clka => clka,
clkb => clkb,
dina => dina,
dinb => dinb,
douta => douta,
doutb => doutb,
wea => wea,
web => web);
-- The following code must appear in the VHDL architecture header:
component graph_mem
port (
clka: IN std_logic;
dina: IN std_logic_VECTOR(3 downto 0);
addra: IN std_logic_VECTOR(15 downto 0);
wea: IN std_logic_VECTOR(0 downto 0);
clkb: IN std_logic;
addrb: IN std_logic_VECTOR(15 downto 0);
doutb: OUT std_logic_VECTOR(3 downto 0));
end component;
-------------------------------------------------------------
-- The following code must appear in the VHDL architecture body.
-- Substitute your own instance name and net names.
your_instance_name : graph_mem
port map (
clka => clka,
dina => dina,
addra => addra,
wea => wea,
clkb => clkb,
addrb => addrb,
doutb => doutb);
-- The following code must appear in the VHDL architecture header:
component lcd_ram
port (
clka: IN std_logic;
dina: IN std_logic_VECTOR(3 downto 0);
addra: IN std_logic_VECTOR(14 downto 0);
wea: IN std_logic_VECTOR(0 downto 0);
clkb: IN std_logic;
addrb: IN std_logic_VECTOR(14 downto 0);
doutb: OUT std_logic_VECTOR(3 downto 0));
end component;
-------------------------------------------------------------
-- The following code must appear in the VHDL architecture body.
-- Substitute your own instance name and net names.
your_instance_name : lcd_ram
port map (
clka => clka,
dina => dina,
addra => addra,
wea => wea,
clkb => clkb,
addrb => addrb,
doutb => doutb);
-- The following code must appear in the VHDL architecture header:
component mem_text_lcd
port (
clka: IN std_logic;
dina: IN std_logic_VECTOR(15 downto 0);
addra: IN std_logic_VECTOR(9 downto 0);
wea: IN std_logic_VECTOR(0 downto 0);
clkb: IN std_logic;
addrb: IN std_logic_VECTOR(9 downto 0);
doutb: OUT std_logic_VECTOR(15 downto 0));
end component;
-------------------------------------------------------------
-- The following code must appear in the VHDL architecture body.
-- Substitute your own instance name and net names.
your_instance_name : mem_text_lcd
port map (
clka => clka,
dina => dina,
addra => addra,
wea => wea,
clkb => clkb,
addrb => addrb,
doutb => doutb);
-- The following code must appear in the VHDL architecture header:
component graph_mem_lcd
port (
clka: IN std_logic;
dina: IN std_logic_VECTOR(0 downto 0);
addra: IN std_logic_VECTOR(15 downto 0);
wea: IN std_logic_VECTOR(0 downto 0);
clkb: IN std_logic;
addrb: IN std_logic_VECTOR(15 downto 0);
doutb: OUT std_logic_VECTOR(0 downto 0));
end component;
-------------------------------------------------------------
-- The following code must appear in the VHDL architecture body.
-- Substitute your own instance name and net names.
your_instance_name : graph_mem_lcd
port map (
clka => clka,
dina => dina,
addra => addra,
wea => wea,
clkb => clkb,
addrb => addrb,
doutb => doutb);