-- PicoBlaze loadable ROM by -cm
-- Definition of a single port ROM for KCPSM3 program defined by pico_rom.psm
--
-- Standard IEEE libraries
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
--
-- The Unisim Library is used to define Xilinx primitives. It is also used during
-- simulation. The source can be viewed at %XILINX%\vhdl\src\unisims\unisim_VCOMP.vhd
--  
library unisim;
use unisim.vcomponents.all;
--
--
entity pb_lcrom is
    Port (pb_address : in std_logic_vector(9 downto 0);
			LC_addr : in std_logic_vector(9 downto 0);
			pb_instruction : out std_logic_vector(17 downto 0);
			pb_clk : in std_logic;
			LC_data: in std_logic_vector(17 downto 0);
			LC_WEN : in std_logic
			); 
    end pb_lcrom;

architecture behave of pb_lcrom is
--  <-----Cut code below this line and paste into the architecture body---->

   -- RAMB16_S18_S18: Virtex-II/II-Pro, Spartan-3/3E 1k x 16 + 2 Parity bits Dual-Port RAM
   -- Xilinx HDL Language Template, version 10.1.2

begin
--
  --Instantiate the Xilinx primitive for a block RAM
   RAMB16_S18_S18_inst : RAMB16_S18_S18
   generic map (
      INIT_A => X"00000", --  Value of output RAM registers on Port A at startup
      INIT_B => X"00000", --  Value of output RAM registers on Port B at startup
      SRVAL_A => X"00000", --  Port A ouput value upon SSR assertion
      SRVAL_B => X"00000", --  Port B ouput value upon SSR assertion
      WRITE_MODE_A => "WRITE_FIRST", --  WRITE_FIRST, READ_FIRST or NO_CHANGE
      WRITE_MODE_B => "WRITE_FIRST", --  WRITE_FIRST, READ_FIRST or NO_CHANGE
      SIM_COLLISION_CHECK => "ALL") -- "NONE", "WARNING", "GENERATE_X_ONLY", "ALL"
      -- keine INITs, RAM vorerst leer
   port map (
      DOA => pb_instruction(15 downto 0),      -- Port A 16-bit Data Output
      DOB => open,      -- Port B 16-bit Data Output
      DOPA => pb_instruction(17 downto 16),    -- Port A 2-bit Parity Output
      DOPB => open,    -- Port B 2-bit Parity Output
      ADDRA =>pb_address,  -- Port A 10-bit Address Input
      ADDRB => LC_addr,  -- Port B 10-bit Address Input
      CLKA => pb_clk,    -- Port A Clock
      CLKB => not LC_WEN,    -- Port B Clock
      DIA => "0000000000000000",      -- Port A 16-bit Data Input
      DIB => LC_data(15 downto 0),      -- Port B 16-bit Data Input
      DIPA => "00",    -- Port A 2-bit parity Input
      DIPB => LC_data(17 downto 16),    -- Port-B 2-bit parity Input
      ENA => '1',      -- Port A RAM Enable Input
      ENB => '1',      -- PortB RAM Enable Input
      SSRA => '0',    -- Port A Synchronous Set/Reset Input
      SSRB => '0',    -- Port B Synchronous Set/Reset Input
      WEA => '0',      -- Port A Write Enable Input
      WEB => '1'       -- Port B Write Enable Input
   );	
end behave;