--------------------------------------------------------------------------------
-- Copyright (c) 1995-2007 Xilinx, Inc.  All rights reserved.
--------------------------------------------------------------------------------
--   ____  ____ 
--  /   /\/   / 
-- /___/  \  /    Vendor: Xilinx 
-- \   \   \/     Version : 9.2.04i
--  \   \         Application : 
--  /   /         Filename : LEDblink.vhd
-- /___/   /\     Timestamp : 04/26/2008 10:35:23
-- \   \  /  \ 
--  \___\/\___\ 
--
--Command: 
--Design Name: LEDblink
--
-- LEDblink lässt LED am Ausgang TestLED blinken

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;


entity led_blinker is
  port
  (
    ClkIn : in std_logic;
    TestLED : out std_logic
  );
end led_blinker;

architecture RTL of led_blinker is

signal timer	: std_logic_vector(23 downto 0);

begin

TestLED<= timer(23) or timer(21);

process(ClkIn)
begin
	if rising_edge(ClkIn) then
		timer <= timer + 1;
	end if;
end process;

end RTL;