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Release 13.1 Trace  (nt64)
Copyright (c) 1995-2011 Xilinx, Inc.  All rights reserved.

C:\Xilinx\13.1\ISE_DS\ISE\bin\nt64\unwrapped\trce.exe -intstyle ise -v 3 -s 4
-n 3 -fastpaths -xml main.twx main.ncd -o main.twr main.pcf

Design file:              main.ncd
Physical constraint file: main.pcf
Device,package,speed:     xc3s50a,vq100,-4 (PRODUCTION 1.41 2011-02-03)
Report level:             verbose report

Environment Variable      Effect 
--------------------      ------ 
NONE                      No environment variables were set
--------------------------------------------------------------------------------

INFO:Timing:2698 - No timing constraints found, doing default enumeration.
INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths 
   option. All paths that are not constrained will be reported in the 
   unconstrained paths section(s) of the report.
INFO:Timing:3339 - The clock-to-out numbers in this timing report are based on 
   a 50 Ohm transmission line loading model.  For the details of this model, 
   and for more information on accounting for different loading conditions, 
   please see the device datasheet.
INFO:Timing:3390 - This architecture does not support a default System Jitter 
   value, please add SYSTEM_JITTER constraint to the UCF to modify the Clock 
   Uncertainty calculation.
INFO:Timing:3389 - This architecture does not support 'Discrete Jitter' and 
   'Phase Error' calculations, these terms will be zero in the Clock 
   Uncertainty calculation.  Please make appropriate modification to 
   SYSTEM_JITTER to account for the unsupported Discrete Jitter and Phase 
   Error.



Data Sheet report:
-----------------
All values displayed in nanoseconds (ns)

Setup/Hold to clock CLK_50MHZ
------------+------------+------------+------------------+--------+
            |Max Setup to|Max Hold to |                  | Clock  |
Source      | clk (edge) | clk (edge) |Internal Clock(s) | Phase  |
------------+------------+------------+------------------+--------+
AUXPORT<0>  |    1.609(R)|   -0.480(R)|XLXN_773          |   0.000|
AUXPORT<1>  |    1.683(R)|   -0.539(R)|XLXN_773          |   0.000|
AUXPORT<2>  |    1.266(R)|   -0.208(R)|XLXN_773          |   0.000|
AUXPORT<3>  |    1.204(R)|   -0.159(R)|XLXN_773          |   0.000|
AUXPORT<4>  |    1.822(R)|   -0.676(R)|XLXN_773          |   0.000|
AUXPORT<5>  |    1.450(R)|   -0.379(R)|XLXN_773          |   0.000|
AUXPORT<6>  |    1.293(R)|   -0.237(R)|XLXN_773          |   0.000|
AUXPORT<7>  |    1.286(R)|   -0.232(R)|XLXN_773          |   0.000|
AUXPORT<8>  |    1.594(R)|   -0.503(R)|XLXN_773          |   0.000|
AUXPORT<9>  |    1.974(R)|   -0.807(R)|XLXN_773          |   0.000|
AUXPORT<10> |    1.375(R)|   -0.286(R)|XLXN_773          |   0.000|
AUXPORT<11> |    1.313(R)|   -0.237(R)|XLXN_773          |   0.000|
AUXPORT<12> |    0.991(R)|   -0.010(R)|XLXN_773          |   0.000|
AUXPORT<13> |    0.954(R)|    0.019(R)|XLXN_773          |   0.000|
AUXPORT<14> |    1.458(R)|   -0.360(R)|XLXN_773          |   0.000|
AUXPORT<15> |    1.396(R)|   -0.311(R)|XLXN_773          |   0.000|
------------+------------+------------+------------------+--------+

Setup/Hold to clock F_SCK
------------+------------+------------+------------------+--------+
            |Max Setup to|Max Hold to |                  | Clock  |
Source      | clk (edge) | clk (edge) |Internal Clock(s) | Phase  |
------------+------------+------------+------------------+--------+
F_MOSI      |    2.329(R)|    0.029(R)|F_SCK_BUFGP       |   0.000|
------------+------------+------------+------------------+--------+

Clock CLK_50MHZ to Pad
------------+------------+------------------+--------+
            | clk (edge) |                  | Clock  |
Destination |   to PAD   |Internal Clock(s) | Phase  |
------------+------------+------------------+--------+
AUXPORT<0>  |    7.868(R)|XLXN_773          |   0.000|
AUXPORT<1>  |    7.790(R)|XLXN_773          |   0.000|
AUXPORT<2>  |    8.159(R)|XLXN_773          |   0.000|
AUXPORT<3>  |    8.111(R)|XLXN_773          |   0.000|
AUXPORT<4>  |    8.319(R)|XLXN_773          |   0.000|
AUXPORT<5>  |    8.906(R)|XLXN_773          |   0.000|
AUXPORT<6>  |    8.021(R)|XLXN_773          |   0.000|
AUXPORT<7>  |    8.193(R)|XLXN_773          |   0.000|
AUXPORT<8>  |    8.352(R)|XLXN_773          |   0.000|
AUXPORT<9>  |    8.363(R)|XLXN_773          |   0.000|
AUXPORT<10> |    8.016(R)|XLXN_773          |   0.000|
AUXPORT<11> |    7.902(R)|XLXN_773          |   0.000|
AUXPORT<12> |    8.001(R)|XLXN_773          |   0.000|
AUXPORT<13> |    8.054(R)|XLXN_773          |   0.000|
AUXPORT<14> |    7.897(R)|XLXN_773          |   0.000|
AUXPORT<15> |    8.346(R)|XLXN_773          |   0.000|
------------+------------+------------------+--------+

Clock F_SCK to Pad
------------+------------+------------------+--------+
            | clk (edge) |                  | Clock  |
Destination |   to PAD   |Internal Clock(s) | Phase  |
------------+------------+------------------+--------+
F_MISO      |    7.536(R)|F_SCK_BUFGP       |   0.000|
------------+------------+------------------+--------+

Clock to Setup on destination clock CLK_50MHZ
---------------+---------+---------+---------+---------+
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
CLK_50MHZ      |    4.199|         |         |         |
F_DS           |    4.579|    2.231|         |         |
F_RS           |    9.114|    1.178|         |         |
---------------+---------+---------+---------+---------+

Clock to Setup on destination clock F_DS
---------------+---------+---------+---------+---------+
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
F_SCK          |    1.464|         |         |         |
---------------+---------+---------+---------+---------+

Clock to Setup on destination clock F_RS
---------------+---------+---------+---------+---------+
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
F_SCK          |    1.821|         |         |         |
---------------+---------+---------+---------+---------+

Clock to Setup on destination clock F_SCK
---------------+---------+---------+---------+---------+
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
F_DS           |    3.694|    3.694|         |         |
F_RS           |    1.734|    1.734|         |         |
F_SCK          |    1.899|         |         |         |
---------------+---------+---------+---------+---------+

Pad to Pad
---------------+---------------+---------+
Source Pad     |Destination Pad|  Delay  |
---------------+---------------+---------+
AUXPORT<0>     |TestLED        |    6.360|
F_DS           |F_MISO         |    8.176|
---------------+---------------+---------+


Analysis completed Mon Nov 14 14:33:03 2011 
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Trace Settings:
-------------------------
Trace Settings 

Peak Memory Usage: 171 MB