--------------------------------------------------------------------------------
-- Copyright (c) 1995-2011 Xilinx, Inc.  All rights reserved.
--------------------------------------------------------------------------------
--   ____  ____ 
--  /   /\/   / 
-- /___/  \  /    Vendor: Xilinx 
-- \   \   \/     Version : 13.1
--  \   \         Application : sch2hdl
--  /   /         Filename : main.vhf
-- /___/   /\     Timestamp : 11/14/2011 14:32:20
-- \   \  /  \ 
--  \___\/\___\ 
--
--Command: sch2hdl -intstyle ise -family spartan3a -flat -suppress -vhdl E:/Dropbox/UNIC_3A/ports/main/main.vhf -w E:/Dropbox/UNIC_3A/ports/source/main.sch
--Design Name: main
--Device: spartan3a
--Purpose:
--    This vhdl netlist is translated from an ECS schematic. It can be 
--    synthesized and simulated, but it should not be modified. 
--

library ieee;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.ALL;
library UNISIM;
use UNISIM.Vcomponents.ALL;

entity main is
   port ( CLK_50MHZ : in    std_logic; 
          F_DS      : in    std_logic; 
          F_MOSI    : in    std_logic; 
          F_RS      : in    std_logic; 
          F_SCK     : in    std_logic; 
          F_MISO    : out   std_logic; 
          TestLED   : out   std_logic; 
          AUXPORT   : inout std_logic_vector (15 downto 0));
end main;

architecture BEHAVIORAL of main is
   attribute BOX_TYPE         : string ;
   attribute IOSTANDARD       : string ;
   attribute IBUF_DELAY_VALUE : string ;
   signal DDRS                   : std_logic_vector (31 downto 0);
   signal PORTS                  : std_logic_vector (31 downto 0);
   signal READPORT               : std_logic_vector (31 downto 0);
   signal XLXN_759               : std_logic_vector (31 downto 0);
   signal XLXN_765               : std_logic_vector (31 downto 0);
   signal XLXN_771               : std_logic_vector (3 downto 0);
   signal XLXN_773               : std_logic;
   signal XLXI_311_D2_openSignal : std_logic_vector (31 downto 0);
   component BUF
      port ( I : in    std_logic; 
             O : out   std_logic);
   end component;
   attribute BOX_TYPE of BUF : component is "BLACK_BOX";
   
   component IBUFG
      port ( I : in    std_logic; 
             O : out   std_logic);
   end component;
   attribute IOSTANDARD of IBUFG : component is "DEFAULT";
   attribute IBUF_DELAY_VALUE of IBUFG : component is "0";
   attribute BOX_TYPE of IBUFG : component is "BLACK_BOX";
   
   component SPI_inout
      port ( SYSCLK : in    std_logic; 
             SCK    : in    std_logic; 
             MOSI   : in    std_logic; 
             DS_N   : in    std_logic; 
             RS_N   : in    std_logic; 
             ADDR   : in    std_logic_vector (3 downto 0); 
             D0     : in    std_logic_vector (31 downto 0); 
             D1     : in    std_logic_vector (31 downto 0); 
             D2     : in    std_logic_vector (31 downto 0); 
             D3     : in    std_logic_vector (31 downto 0); 
             STR0   : out   std_logic; 
             STR1   : out   std_logic; 
             STR2   : out   std_logic; 
             STR3   : out   std_logic; 
             MISO   : out   std_logic; 
             Q0     : out   std_logic_vector (31 downto 0); 
             Q1     : out   std_logic_vector (31 downto 0); 
             Q2     : out   std_logic_vector (31 downto 0); 
             Q3     : out   std_logic_vector (31 downto 0));
   end component;
   
   component PORT_DDR
      port ( SYSCLK  : in    std_logic; 
             DQ      : in    std_logic_vector (15 downto 0); 
             DDR     : in    std_logic_vector (15 downto 0); 
             OUTPORT : out   std_logic_vector (15 downto 0));
   end component;
   
begin
   XLXN_759(31 downto 0) <= x"21062011";
   XLXN_765(31 downto 0) <= x"AA550000";
   XLXN_771(3 downto 0) <= x"0";
   XLXI_186 : BUF
      port map (I=>READPORT(0),
                O=>TestLED);
   
   XLXI_275 : IBUFG
      port map (I=>CLK_50MHZ,
                O=>XLXN_773);
   
   XLXI_311 : SPI_inout
      port map (ADDR(3 downto 0)=>XLXN_771(3 downto 0),
                DS_N=>F_DS,
                D0(31 downto 0)=>XLXN_765(31 downto 0),
                D1(31 downto 0)=>XLXN_759(31 downto 0),
                D2(31 downto 0)=>XLXI_311_D2_openSignal(31 downto 0),
                D3(31 downto 0)=>READPORT(31 downto 0),
                MOSI=>F_MOSI,
                RS_N=>F_RS,
                SCK=>F_SCK,
                SYSCLK=>XLXN_773,
                MISO=>F_MISO,
                Q0=>open,
                Q1=>open,
                Q2(31 downto 0)=>DDRS(31 downto 0),
                Q3(31 downto 0)=>PORTS(31 downto 0),
                STR0=>open,
                STR1=>open,
                STR2=>open,
                STR3=>open);
   
   XLXI_314 : PORT_DDR
      port map (DDR(15 downto 0)=>DDRS(15 downto 0),
                DQ(15 downto 0)=>PORTS(15 downto 0),
                SYSCLK=>XLXN_773,
                OUTPORT(15 downto 0)=>AUXPORT(15 downto 0));
   
   XLXI_317_0 : BUF
      port map (I=>AUXPORT(0),
                O=>READPORT(0));
   
   XLXI_317_1 : BUF
      port map (I=>AUXPORT(1),
                O=>READPORT(1));
   
   XLXI_317_2 : BUF
      port map (I=>AUXPORT(2),
                O=>READPORT(2));
   
   XLXI_317_3 : BUF
      port map (I=>AUXPORT(3),
                O=>READPORT(3));
   
   XLXI_317_4 : BUF
      port map (I=>AUXPORT(4),
                O=>READPORT(4));
   
   XLXI_317_5 : BUF
      port map (I=>AUXPORT(5),
                O=>READPORT(5));
   
   XLXI_317_6 : BUF
      port map (I=>AUXPORT(6),
                O=>READPORT(6));
   
   XLXI_317_7 : BUF
      port map (I=>AUXPORT(7),
                O=>READPORT(7));
   
   XLXI_317_8 : BUF
      port map (I=>AUXPORT(8),
                O=>READPORT(8));
   
   XLXI_317_9 : BUF
      port map (I=>AUXPORT(9),
                O=>READPORT(9));
   
   XLXI_317_10 : BUF
      port map (I=>AUXPORT(10),
                O=>READPORT(10));
   
   XLXI_317_11 : BUF
      port map (I=>AUXPORT(11),
                O=>READPORT(11));
   
   XLXI_317_12 : BUF
      port map (I=>AUXPORT(12),
                O=>READPORT(12));
   
   XLXI_317_13 : BUF
      port map (I=>AUXPORT(13),
                O=>READPORT(13));
   
   XLXI_317_14 : BUF
      port map (I=>AUXPORT(14),
                O=>READPORT(14));
   
   XLXI_317_15 : BUF
      port map (I=>AUXPORT(15),
                O=>READPORT(15));
   
end BEHAVIORAL;