Release 13.1 Map O.40d (nt64) Xilinx Mapping Report File for Design 'main' Design Information ------------------ Command Line : map -intstyle ise -p xc3s50a-vq100-4 -cm area -ir off -pr off -c 100 -o main_map.ncd main.ngd main.pcf Target Device : xc3s50a Target Package : vq100 Target Speed : -4 Mapper Version : spartan3a -- $Revision: 1.55 $ Mapped Date : Mon Nov 14 14:32:44 2011 Design Summary -------------- Number of errors: 0 Number of warnings: 0 Logic Utilization: Number of Slice Flip Flops: 167 out of 1,408 11% Number of 4 input LUTs: 62 out of 1,408 4% Logic Distribution: Number of occupied Slices: 132 out of 704 18% Number of Slices containing only related logic: 132 out of 132 100% Number of Slices containing unrelated logic: 0 out of 132 0% *See NOTES below for an explanation of the effects of unrelated logic. Total Number of 4 input LUTs: 62 out of 1,408 4% Number of bonded IOBs: 23 out of 68 33% Number of BUFGMUXs: 4 out of 24 16% Average Fanout of Non-Clock Nets: 1.72 Peak Memory Usage: 242 MB Total REAL time to MAP completion: 2 secs Total CPU time to MAP completion: 2 secs NOTES: Related logic is defined as being logic that shares connectivity - e.g. two LUTs are "related" if they share common inputs. When assembling slices, Map gives priority to combine logic that is related. Doing so results in the best timing performance. Unrelated logic shares no connectivity. Map will only begin packing unrelated logic into a slice once 99% of the slices are occupied through related logic packing. Note that once logic distribution reaches the 99% level through related logic packing, this does not mean the device is completely utilized. Unrelated logic packing will then begin, continuing until all usable LUTs and FFs are occupied. Depending on your timing budget, increased levels of unrelated logic packing may adversely affect the overall timing performance of your design. Table of Contents ----------------- Section 1 - Errors Section 2 - Warnings Section 3 - Informational Section 4 - Removed Logic Summary Section 5 - Removed Logic Section 6 - IOB Properties Section 7 - RPMs Section 8 - Guide Report Section 9 - Area Group and Partition Summary Section 10 - Timing Report Section 11 - Configuration String Information Section 12 - Control Set Information Section 13 - Utilization by Hierarchy Section 1 - Errors ------------------ Section 2 - Warnings -------------------- WARNING:Security:43 - No license file was found in the standard Xilinx license directory. WARNING:Security:44 - No license file was found. WARNING:Security:42 - Your software subscription period has lapsed. Your current version of Xilinx tools will continue to function, but you no longer qualify for Xilinx software updates or new releases. Section 3 - Informational ------------------------- INFO:Security:50 - The XILINXD_LICENSE_FILE environment variable is set to 'C:\Xilinx\Xilinx.lic'. INFO:Security:53 - The LM_LICENSE_FILE environment variable is not set. INFO:Security:54 - 'xc3s50a' is a WebPack part. INFO:MapLib:562 - No environment variables are currently set. INFO:LIT:244 - All of the single ended outputs in this design are using slew rate limited output drivers. The delay on speed critical single ended outputs can be dramatically reduced by designating them as fast outputs. Section 4 - Removed Logic Summary --------------------------------- 2 block(s) optimized away Section 5 - Removed Logic ------------------------- Optimized Block(s): TYPE BLOCK GND XST_GND VCC XST_VCC To enable printing of redundant blocks removed and signals merged, set the detailed map report option and rerun map. Section 6 - IOB Properties -------------------------- +-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ | IOB Name | Type | Direction | IO Standard | Diff | Drive | Slew | Reg (s) | Resistor | IBUF/IFD | SUSPEND | | | | | | Term | Strength | Rate | | | Delay | | +-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ | AUXPORT<0> | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | | | 0 / 0 | 3STATE | | AUXPORT<1> | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | | | 0 / 0 | 3STATE | | AUXPORT<2> | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | | | 0 / 0 | 3STATE | | AUXPORT<3> | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | | | 0 / 0 | 3STATE | | AUXPORT<4> | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | | | 0 / 0 | 3STATE | | AUXPORT<5> | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | | | 0 / 0 | 3STATE | | AUXPORT<6> | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | | | 0 / 0 | 3STATE | | AUXPORT<7> | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | | | 0 / 0 | 3STATE | | AUXPORT<8> | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | | | 0 / 0 | 3STATE | | AUXPORT<9> | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | | | 0 / 0 | 3STATE | | AUXPORT<10> | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | | | 0 / 0 | 3STATE | | AUXPORT<11> | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | | | 0 / 0 | 3STATE | | AUXPORT<12> | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | | | 0 / 0 | 3STATE | | AUXPORT<13> | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | | | 0 / 0 | 3STATE | | AUXPORT<14> | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | | | 0 / 0 | 3STATE | | AUXPORT<15> | IOB | BIDIR | LVCMOS33 | | 12 | SLOW | | | 0 / 0 | 3STATE | | CLK_50MHZ | IBUF | INPUT | LVCMOS33 | | | | | | 0 / 0 | | | F_DS | IBUF | INPUT | LVCMOS33 | | | | | | 0 / 0 | | | F_MISO | IOB | OUTPUT | LVCMOS33 | | 12 | SLOW | | | 0 / 0 | 3STATE | | F_MOSI | IBUF | INPUT | LVCMOS33 | | | | | | 0 / 0 | | | F_RS | IBUF | INPUT | LVCMOS33 | | | | | | 0 / 0 | | | F_SCK | IBUF | INPUT | LVCMOS33 | | | | | | 0 / 0 | | | TestLED | IOB | OUTPUT | LVCMOS33 | | 12 | SLOW | | | 0 / 0 | 3STATE | +-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ Section 7 - RPMs ---------------- Section 8 - Guide Report ------------------------ Guide not run on this design. Section 9 - Area Group and Partition Summary -------------------------------------------- Partition Implementation Status ------------------------------- No Partitions were found in this design. ------------------------------- Area Group Information ---------------------- No area groups were found in this design. ---------------------- Section 10 - Timing Report -------------------------- This design was not run using timing mode. Section 11 - Configuration String Details ----------------------------------------- Use the "-detail" map option to print out Configuration Strings Section 12 - Control Set Information ------------------------------------ No control set information for this architecture. Section 13 - Utilization by Hierarchy ------------------------------------- Use the "-detail" map option to print out the Utilization by Hierarchy section.