--------------------------------------------------------------------------------
-- Copyright (c) 1995-2007 Xilinx, Inc.  All rights reserved.
--------------------------------------------------------------------------------
--   ____  ____ 
--  /   /\/   / 
-- /___/  \  /    Vendor: Xilinx 
-- \   \   \/     Version : 9.2.04i
--  \   \         Application : 
--  /   /         Filename : LEDblink.vhd
-- /___/   /\     Timestamp : 04/26/2008 10:35:23
-- \   \  /  \ 
--  \___\/\___\ 
--
--Command: 
--Design Name: LEDblink
--
-- LEDblink lässt LED am Ausgang TestLED blinken

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;


entity ledpwm is
  port
  (
    SYSCLK : in std_logic;
	 PWM : in std_logic_vector (7 downto 0);
    LED : out std_logic
  );
end ledpwm;

architecture RTL of ledpwm is

signal timer	: std_logic_vector(11 downto 0);

begin

process(SYSCLK)
begin
	if rising_edge(SYSCLK) then
		timer <= timer + 1;
		if timer(11 downto 4) < PWM then
			LED<='0';
		else
			LED<='1';
		end if;		
	end if;
end process;


end RTL;