Design Rule Check Report ------------------------ Report File : H:\ProjPCB\ADAC\FPGA-ISRAM_BGA\FPGA (PCB - Design Rule Check Report).txt Report Written : Sunday, August 15, 2010 Design Path : H:\ProjPCB\ADAC\FPGA-ISRAM_BGA\FPGA.pcb Design Title : Created : 14.12.2006 11:34:15 Last Saved : 15.08.2010 13:24:26 Editing Time : 35431 min Units : mm (precision 2) Results ------- Pad to Board Error (P-B) between (47.31 205.74) and (45.47 205.74) on Layer "[All]". Error between Pad (Net 'Iso') and Board, Gap is 1.74 needs to be 1.91. Pad to Board Error (P-B) between (47.31 116.84) and (45.47 116.84) on Layer "[All]". Error between Pad (Net 'Iso') and Board, Gap is 1.74 needs to be 1.91. Pad to Board Error (P-B) between (205.40 171.05) and (205.87 171.05) on Layer "[All]". Error between Component Pad PL16.12 (Net 'DGnd') and Board, Gap is 0.37 needs to be 1.91. Pad to Board Error (P-B) between (205.40 196.83) and (205.87 196.83) on Layer "[All]". Error between Component Pad PL16.13 (Net 'DGnd') and Board, Gap is 0.37 needs to be 1.91. Via to Board Error (V-B) between (47.33 136.21) and (45.47 136.21) on Layer "[All]". Error between Via (Net 'N3417!FPGA-RTC!') and Board, Gap is 1.76 needs to be 2.00. Number of errors found : 5 Accepted Errors already in the design ------------------------------------- Number of errors found : 1 Component to Component error (Cm-Cm) at (76.52 172.68) on layer "[Bottom]". C16 - C26, Gap is 0.00. Settings -------- Spacings Tracks Yes Pads and Vias Yes Shapes Yes Text No Board Yes Drills Yes Components No Manufacturing Drill Breakout No Drill Backoff No Silkscreen Overlap No Wires No Component Height No Copper Text In Board No Min Track Width Yes Neck Length No Min Annular Ring No Min Paste Size No Vias In Pads No Unplated Vias No Unplated Pads With Inner Tracks No Nets Net Completion No Dangling Tracks No Net Track Length Differences No End Of Report.